Multichannel FILO data buffer storage devices

Abstract

A data buffer storing device of first in first out with multichannel, used for carrying on FIFO data buffering for each of buffering data coming from the multichannel includes data storing unit, read / write pointer control unit and state labelling unit, of which the data storing unit only applies a dual port RAM (R1) and the read / write pointer control for each channel is also integrated separately into one read / write pointer control unit so as to decrease the resources for a large number of read / write pointer counter as well as to simplify the complicacy of interface logic.

Description

technical field [0001] The present invention relates to a kind of storage bank realization using FIFO (First In First Out) mechanism in the design of ASIC (Application Specific Integrated Circuit) or FPGA (Field Programable Gate Array Field Programmable Gate Array) of data communication service A device for multi-channel data buffering. Background technique [0002] At present, in the ASIC or FPGA design of the data communication service, it is often necessary to deal with the data buffering of multiple channels. The usual implementation method is to use a superposition method, that is, to use a FIFO for each channel to buffer. FIFO can also be understood as an abbreviation for a memory bank used for data buffering in ASIC / FPGA design. Usually, three parts are needed to realize the FIFO storage function: data storage unit, read and write pointer control unit and status indication unit. The data storage unit uses dual-port RAM to store data; the read-write pointer control u...

AI Technical Summary

Problems solved by technology

In this case, if the data width of each FIFO is 8bit, and the FIFO depth is 64, in addition to 64 64×8 dual-port RAMs, 64×2 6bits constituting the read and write address pointers will be consumed. counter and 64×6bit data counter

More importantly, the output of 8-bit data of 64 FIFOs also needs a 64×8bit wide multiplexing (MUX) logic, which will consume a large amount of combinational logic resources, and the logic wiring here is also will be very difficult

Therefore, the main frequency of the whole system will be seriously affected

It can be seen that it will become more and more difficult to realize the superposition of FIFO as the number of channels increases.

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