Delay phase-locking loop unit and its clock signal generating method

Abstract

The delay phase-locking loop unit is used to receive a reference clock signal and produce several output clock signals in different phases. It includes one controlled delay circuit, one phase monitor and one control circuit. The production of clock signal includes the following steps: receiving one reference clock signal; phase delaying in the controlled delay circuit and outputting several output clock signals in different phases. The control circuit outputs one regulating signal corresponding to the phase difference between the output clock signal and the reference clock signal; and the controlled delay circuit delays the output signal corresponding to the control signal.

Description

technical field [0001] The invention relates to a delay-locked loop device and a clock signal generating method, in particular to a delay-locked loop device and a clock signal generating method applied in a core logic circuit chip. Background technique [0002] In the personal computer architecture, apart from the central processing unit, the components that most affect the data processing performance are the core logic chip and the memory module. Please refer to FIG. 1(a), which is a functional block diagram of a core logic chip 10 connected to a memory module 11. Under the double data transfer rate (DDR) specification, when the core logic chip 10 is to parallel a When data is transmitted to the memory module 11, the core logic chip 10 needs to transmit a strobe signal (strobe) together with a parallel data signal (TX_D) to the memory module 11 outside the chip, and then provide the memory module 11 to read data When used, please refer to Figure 1(b) for the ideal waveform...

AI Technical Summary

Problems solved by technology

[0004] Since the count value received by each controlled delay line in the controlled delay circuit 21 is the same, it can be ensured that the phases of the four output clock signals can be evenly distributed and have a difference of 90 degrees every two, but this method is different from each time The adjustment action will change a total of 4 delay units. Therefore, the lack of accuracy of the signal delay will cause serious problems when the transmission rate is increased in the future.

In addition, common means can only ensure that the formed parallel data signal (TX_D) is in an ideal state at the source 101, because after these signals are sent out by the source 101, they need to go through different transmission paths to reach the I / O pad group (I / OPad). )102

And because different transmission paths will produce different degrees of delay effect (skew) and interference to these signals, the strobe signal (strobe) and the parallel data signal output by the I / O pad group (I / O Pad) 102 will be The waveform shown in Figure 2(c) may be generated, for example, the rising and falling edges of the strobe signal may not be generated in the middle of the parallel data signal (TX_D)

This may cause data receiving errors at the receiving end of the memory module 11, and this situation will become more serious when the transmission rate is increased. How to improve this defect is the main purpose of the present invention

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