Circuit for recovering timing data and implementing method

Abstract

The invention discloses a method for implementing a clock data recovery circuit, wherein the clock recovery circuit includes: a data phase detection module, a frequency division module by N, a data buffer module and a recovery clock adjustment module; by effectively using the buffer technology of data processing , the clock data of the RZ signal is recovered, so that the recovered clock can be flexibly and quickly locked, and it has good low-frequency and high-frequency debounce characteristics, and can be used for clock data recovery in the process of synchronous data transmission in the communication field.

Description

technical field [0001] The invention relates to a clock data recovery circuit and its realization method, in particular to a clock data recovery circuit and its realization method in E1 data processing in the field of narrowband communication. Background technique [0002] In the field of communication, in order to transmit data synchronously, the clock is usually hidden in the user data. Since the user data has a lot of jitter after being interfered by various external signals, before entering the E1 data processing system, ensure that The stability of the data is very important, so the clock data recovery circuit is widely used in the E1 data processing system in the communication field to ensure the stability of the clock data. [0003] At present, the clock data recovery circuit is usually realized by a digital-analog hybrid circuit. After the user data is converted from analog to digital, the user data and clock are extracted and recovered through the phase-locked loop...

AI Technical Summary

Problems solved by technology

Because analog circuits are usually difficult to verify in pure digital system circuits, many systems have gradually begun to use pure digital phase-locked loops to achieve clock data recovery. However, due to the different implementation methods of various digital circuits, usually There is a situation where the anti-jitter ability of clock data recovery is relatively poor at low frequencies

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