Method for making grid and MOS transistor

Abstract

This invention provides a method for processing grid and MOS on a semiconductor substrate, the surface of which includes a first oxidation layer, a conduction layer, a metal silicide layer and a mask layer. The method includes: firstly, defining the said grid pattern on the mask, then to etch to remove the said metal silicide layer and the conducting layer uncovered by the mask, then to oxide the surface to form a second oxidation layer on the first, finally to carry out a wet etching to remove part of the silicide layer to make both sides of it with curved structures and etch back the said oxidation layer.

Description

technical field [0001] The present invention relates to a kind of method making gate and metal oxide semiconductor (MOS) transistor on semiconductor substrate, relate in particular to a kind of method making gate and MOS transistor on semiconductor substrate, and this method can improve The disadvantage of gate sidewall protrusion caused by fire process. Background technique [0002] The fabrication of semiconductor integrated circuits involves many processing steps, such as masking, photoresist coating, etching and deposition. With the development of science and technology, in advanced semiconductor technology, it is constantly required to increase the density of integrated circuits and squeeze more transistors into a limited area. There are as many as hundreds of thousands of transistors. In order to avoid the mutual interference between the operations of the transistors under this condition, or even a short circuit (short circuit), it is necessary to develop various meth...

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Problems solved by technology

[0007] In addition, when using dry etching to define the outlines of the gates 24, 26, the semiconductor chip 10 is very likely to affect the uniformity of the entire etching due to micro-loading effects, such as pattern-dense areas on the semiconductor chip. (dense region) and the gate line width on the pattern isolation region (isolation region), it is difficult to form a symmetrical gate sidewall profile by dry etching, so this is also a problem that needs to be improved urgently in the prior art

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