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Multi-way cache apparatus and method

A buffer memory, ultra-high-speed technology, applied in memory systems, instruments, memory architecture access/allocation, etc., can solve problems such as cache memory access failures, reduce cache memory efficiency, etc., and achieve the effect of saving power consumption

Inactive Publication Date: 2004-12-01
FREESCALE SEMICON INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] According to the existing cache memory technology, in many applications, the efficiency of the cache memory is reduced by the conflict of access requests, wherein the conflict of access requests causes multiple access failures to the cache memory and requires access to external memory

Method used

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  • Multi-way cache apparatus and method
  • Multi-way cache apparatus and method
  • Multi-way cache apparatus and method

Examples

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Embodiment Construction

[0017] It should be noted that the specific terms and expressions used herein, the specific structural and operational details described in the detailed description, and the accompanying drawings are for illustrative purposes only and do not limit The scope of the invention described.

[0018] see figure 1 , illustrates one embodiment of the processing system 10 . Processing system 10 includes a processor 12 , and an external memory 14 . Processor 12 includes a central processing unit 16 , a cache memory 18 , a bus interface 22 , and other modules 20 . Processor 12 also includes bus 24 and bus 26 . Bus 24 interconnects CPU 16 , cache memory 18 , bus interface 22 , and other modules 20 together. Bus 26 couples bus interface 22 and memory 14 together. Although one particular embodiment of a data processing system has been described, various configurations and other embodiments for such a processing system may be implemented. For example, although cache memory 18 is shown a...

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Abstract

Apparatus having a multi-way cache , the apparatus including a first user controllable element having a predetermined first attribute corresponding to a first way of the multi-way cache; a second user controllable element having a predetermined second attribute corresponding to a second way of the multi-way cache; first and second compare circuitry which compare the access attribute to the predetermined first or second attribute to provide a first or second comparison result; first and second way control circuitry for selectively enabling the first or second way of the multi-way cache based on the first or second comparison result.

Description

technical field [0001] The present invention relates generally to processors and memories, and more particularly to multi-way cache memories. Background technique [0002] Due to the widespread use of portable and hand-held tools, low power consumption has become very important in the design of microprocessors and microcontrollers. A typical embedded control system generally includes a central processing unit (CPU) and multiple different types of memory and peripheral devices. Different types of memory may be external to and / or within the same integrated circuit with the microprocessor, and different types of memory may include cache memory, ROM (read only memory), and Multiple SRAM (Static Random Access Memory) devices. [0003] It takes a lot of energy and time to access a large external main memory. Therefore, a smaller, faster, more efficient memory, sometimes referred to as cache memory, can be used in integrated circuits to reduce the number of accesses to main memo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08
CPCG06F12/0848Y02B60/1225G06F2212/1028G06F12/0864Y02D10/00G06F12/08
Inventor 威廉·C.·莫耶
Owner FREESCALE SEMICON INC
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