Pulse generator circuit

Abstract

The invention provides a kind of pulse generation circuit which could produce the pulse with high speed and fixed pulse-width and could produce the pulse of the activating basic pulse PG which is suitable for the reading and writing motion from the internal of the synchronized integrated circuit, in particular the semiconductor memory circuit. Said pulse PG makes the transistor pM1 conduct by way of catering the high fringe of the first cycle in the timer clock CLK to produce start fringe, and makes the transistor nM1 conduct by way of catering the high fringe of the second cycle in the timer clock CLK to produce the end fringe of PG. Thus, the time period until producing the pulse is high speed. Since the pulse width is determined by the period, it is not changed completely.

Description

Technical field [0001] The present invention relates to a pulse generating circuit that generates a basic pulse for activating internal read and write operations of a synchronous integrated circuit such as a semiconductor memory circuit, and more particularly to a pulse generating circuit that uses two or more cycles to perform an internal access operation mode. Background technique [0002] Figure 8 It is a circuit diagram showing a conventional pulse generating circuit, Picture 9 Indicates its timing chart. In the latch circuit 20, the internal activation information generated by the operation start signal AC is latched according to the clock signal CLK, and at the same time, the output of the latch circuit 20 and the NAND logic of the clock signal CLK are obtained to generate the information expanded to the lower edge of CLK. Internal signal A. Furthermore, in the NOR circuit 22, the short pulse signal B synchronized with the upper edge of the clock signal CLK is generated ...

AI Technical Summary

Problems solved by technology

Since this circuit is usually composed of inverters connected in multiple stages, there is a disadvantage

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