Method and device for generating FW of CPLD and medium

A technology for generating codes and parameters, applied in the field of hardware development, can solve problems such as language barriers for hardware engineers, achieve the effect of eliminating language barriers and simplifying the design process

Pending Publication Date: 2022-07-22
INSPUR BUSINESS MACHINE CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

CPLD is a special signal logic design chip. The underlying code of chip control needs to be written in Verilog language, which has language barriers for hardware engineers.

Method used

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  • Method and device for generating FW of CPLD and medium
  • Method and device for generating FW of CPLD and medium
  • Method and device for generating FW of CPLD and medium

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Embodiment Construction

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative work fall within the protection scope of the present application.

[0038] CPLD is a commonly used chip for motherboards. Currently, in the development of CPLD, it is necessary to use Verilog language to design the underlying source code of multiple functional modules. The workload is large, and there is a language threshold for hardware engineers. In addition, due to the readability of CPLD source code Therefore, it is inefficient and error-prone to directly rewrite the underlying source code, which is not conduci...

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Abstract

The invention discloses a method and device for generating an FW of a CPLD and a medium, and mainly relates to the field of hardware development. The method comprises the steps of firstly obtaining a parameter document; wherein the parameter document is a pre-written Excel document containing the design requirement of the CPLD; generating a code file according to parameters in the parameter document; and finally, the code file is stored in programming software, so that the programming software can generate the FW according to the code file. Therefore, according to the method, the Excel document is used for collecting various parameters of the CPLD design, so that the various parameters of the CPLD design are visualized. In addition, an engineer does not need to carry out actual compiling of a bottom layer source code, the language threshold of CPLD design is powerfully eliminated, and the CPLD design process is simplified.

Description

technical field [0001] The present application relates to the field of hardware development, and in particular, to a method, device and medium for generating FW of a CPLD. Background technique [0002] Complex Programmable Logic Device (CPLD) is a commonly used chip for server boards, but for ordinary hardware engineers, the development of CPLD in project development has always been a difficult and energy-consuming task. [0003] figure 1 The flow chart of the FW generation method for the traditional CPLD, such as figure 1 As shown, in the development of CPLD, the underlying source code of multiple modules needs to be designed. CPLD is a special signal logic design chip. The underlying code of the chip control needs to be written in Verilog language, which has a language threshold for hardware engineers. [0004] It can be seen that how to lower the language threshold of CPLD development is a problem to be solved urgently by those skilled in the art. SUMMARY OF THE INVE...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/34G06F8/30G06F8/10
CPCG06F8/34G06F8/313G06F8/10
Inventor 王同心
Owner INSPUR BUSINESS MACHINE CO LTD
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