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Wafer-to-wafer interconnection structure and manufacturing method thereof

An interconnection structure and wafer technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., can solve problems such as charging, arc discharge, and wafer damage, and improve productivity and stability, avoiding arc discharge and wafer damage

Pending Publication Date: 2022-07-15
NAN YA TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, prolonged etching of deeper TSVs will lead to charge on the metal etch stop layer of shallower TSVs, and this phenomenon may cause arcing and wafer damage

Method used

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  • Wafer-to-wafer interconnection structure and manufacturing method thereof
  • Wafer-to-wafer interconnection structure and manufacturing method thereof
  • Wafer-to-wafer interconnection structure and manufacturing method thereof

Examples

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Embodiment Construction

[0057] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

[0058] 1A to 1K Shown is a schematic cross-sectional view of the manufacturing process of the wafer-to-wafer interconnect structure according to the first embodiment of the present invention.

[0059] Please refer to Figure 1A, a first substrate 100 is provided, and a first etch stop layer 102 is formed on the first surface 100 a of the first substrate 100 . The first substrate 100 , for example, at least includes a wafer 104 and an insulating layer 106 formed thereon, and a first etch stop layer 102 is formed on the insulating layer 106 . The first etch stop layer 102 includes a first portion 102' and a second portion 102", and the first portion 102' is separated from the second portion 1...

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PUM

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Abstract

A method of fabricating a wafer-to-wafer interconnect structure includes forming a first etch stop layer having at least two portions on a first surface of a first substrate, and forming a void in a portion of the first etch stop layer. The second etch stop layer is formed on the first surface of the second substrate and bonds the first surface of the first substrate with the second substrate, where the second etch stop layer is aligned with the void. By using the first etch stop layer and the second etch stop layer as etch stop layers, a first opening is formed from the second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV is formed in the first opening, and a second TSV is formed in the second opening.

Description

technical field [0001] The present invention relates to a wafer-to-wafer structure and a manufacturing method thereof, in particular to a wafer-to-wafer interconnection structure and a manufacturing method thereof. Background technique [0002] With the advancement of technology, 3D integrated circuit technology has been developed to achieve and increase the demand for semiconductor miniaturization and process cost reduction. In 3D integrated circuits, semiconductor chips can be vertically stacked by techniques such as bonding or packaging, and different chips are connected using Through-silicon vias (TSVs). TSVs can provide vertical conductive paths and can have advantages such as increasing chip stacking density, improving product efficiency and reducing energy consumption. [0003] However, prolonged etching of the deeper TSVs will result in a charge on the metal etch stop layer of the shallower TSVs, and this phenomenon may cause arcing and wafer damage. SUMMARY OF TH...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/48
CPCH01L21/76898H01L23/481H01L24/80H01L25/50H01L2225/06544H01L2225/06524H01L2224/80896H01L2224/8385H01L2224/32145H01L2924/00014H01L23/49827H01L21/486
Inventor 罗翊仁
Owner NAN YA TECH
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