SRAM (Static Random Access Memory) error correction method, system and terminal

An error correction method and error correction system technology, applied in the field of static random access memory, can solve the problems of multiple requirements and self-adaptive adjustments that cannot take into account SRAM power consumption, speed and reliability, and achieve extremely practical and effective error correction , the effect of improving reliability

Pending Publication Date: 2022-07-01
SHANGHAI IND U TECH RES INST
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Problems solved by technology

However, although the refresh frequency (1 / t) in the above-mentioned SRAM error correction method is adjustable, it cannot be adaptively adjusted according to the irradiation situation, so it cannot take into account the multiple requirements of SRAM power consumption, speed and reliability

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  • SRAM (Static Random Access Memory) error correction method, system and terminal
  • SRAM (Static Random Access Memory) error correction method, system and terminal
  • SRAM (Static Random Access Memory) error correction method, system and terminal

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Embodiment Construction

[0038] The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other under the condition of no conflict.

[0039] It should be noted that the drawings provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and number of compo...

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Abstract

The invention provides an SRAM (Static Random Access Memory) error correction method and system and a terminal. The method comprises the following steps: acquiring an ECC (Error Correction Code) value of a bit unit of an SRAM in a refresh cycle; when the ECC value is greater than a preset threshold value, improving the refresh frequency of the SRAM; and when the ECC value is smaller than the preset threshold value, reducing the refresh frequency of the SRAM. According to the SRAM error correction method and system and the terminal, effective error correction of the SRAM is realized by adaptively adjusting the refresh frequency of the SRAM, and the reliability of the SRAM is greatly improved.

Description

technical field [0001] The present invention relates to the technical field of Static Random-Access Memory (SRAM), in particular to an SRAM error correction method, system and terminal. Background technique [0002] SRAM is widely used in computers, servers, communication storage devices, etc. due to its high integration, high speed, and low power consumption. Reliability and data integrity are the most important factors to be concerned with when storing devices, so it is required that the data in the memory cannot be damaged by environmental conditions such as radiation. SRAM is particularly sensitive to single-event upset effects, which can cause unpredictable inversions of data stored in SRAM address cells, with serious consequences. [0003] In order to improve the reliability of SRAM, it is necessary to consider on-chip or off-chip error checking performance or redundancy technology when designing the system. As the size of devices in the semiconductor industry become...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G11C11/413
CPCG11C29/42G11C11/413
Inventor 许霞董业民杨文伟
Owner SHANGHAI IND U TECH RES INST
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