Analog frequency divider

Abstract

The invention discloses an analog frequency divider which comprises a first analog latch and a second analog latch, the output end of the first analog latch is connected with the input end of the second analog latch, and the output end of the second analog latch is connected with the input end of the first analog latch; the analog frequency divider receives analog signals, and the analog signals are amplified and sampled through the first analog latch and the second analog latch so as to realize frequency division of the analog signals. According to the invention, the output end of the first analog latch is connected with the input end of the second analog latch, and the output end of the second analog latch is connected with the input end of the first analog latch, so that the frequency division of the analog signal is realized.

Description

technical field [0001] The present application relates to the field of frequency dividers, in particular to an analog frequency divider. Background technique [0002] In the prior art, high-speed DRAM products generally add a digital clock frequency divider after the received clock signal WCKT / WCKC to reduce the frequency of the clock signal through the digital clock frequency divider in order to solve the upper limit of the frequency of the clock channel. After that, it is passed to subsequent circuits. [0003] With the continuous upgrading of DRAM product interfaces, the frequency of the input clock continues to increase. However, the digital frequency divider has a frequency upper limit, which cannot meet the clock input frequency requirements in high-speed DRAM chips. When the input clock frequency exceeds the upper limit of the operating frequency of the digital frequency divider, the frequency division function is faulty, and the normal frequency division function ca...

AI Technical Summary

Problems solved by technology

[0003] With the continuous upgrading of DRAM product interface, the frequency of input clock is constantly increasing. However, there is an upper frequency limit of digital frequency divider, which cannot meet the requirements of clock input frequency in high-speed DRAM chips.

When the input clock frequency exceeds the upper limit of the operating frequency of the digital frequency divider, the frequency division function will fail, and the normal frequency division function cannot be completed.

Images