Calibration method and system for current density over-standard region of integrated circuit layout

Abstract

The invention discloses an integrated circuit layout current density exceeding area calibration method and system, and belongs to the technical field of integrated circuit electromagnetic field analysis, and the method comprises the steps: carrying out the mesh generation of an integrated circuit layout, employing an electromagnetic field numerical calculation method, and calculating the current density of a mesh unit in each layer of layout; based on the current density of the grid units in each layer of layout, identifying the grid units with the current density exceeding the standard; and identifying connected grid cells by adopting a neighbor search method based on the identified grid cells with the current density exceeding the standard to form connected grid cell regions, and setting edges corresponding to the grid cells without neighbor grid cells as boundaries of the connected grid cell regions for each connected grid cell region. The current density calibration method solves the problems that when the layout shape of the integrated circuit is complex, a traditional current density calibration method is not effective any more, and a current density exceeding area cannot be accurately calibrated, and is beneficial to optimization and rectification of the layout of the large-scale integrated circuit.

Description

technical field [0001] The application belongs to the technical field of integrated circuit electromagnetic field analysis, and in particular relates to a method and system for calibrating an area where the current density of an integrated circuit layout exceeds the standard. Background technique [0002] With the development of communication technology, the research and development of VLSI has gradually started. In order to improve the performance of electronic equipment, reduce the size and reduce the cost, the current production status is to integrate transistors, other components and circuits on a small semiconductor substrate. In order to achieve more functions, VLSIs currently have several to hundreds of layers of structures, each layer is extremely complex, and integrates tens of millions or even hundreds of millions of transistors, and all of them have centimeter-level to the latest nano-level Multiscale structure. Such a complex structure also brings difficulties ...

AI Technical Summary

Problems solved by technology

[0005] At present, the calibration of the area where the current density exceeds the standard on the integrated circuit layout is usually a rectangular area calibration. This calibration method is effective for the layout shape with a simple structure in the early stage, and can quickly identify the position where the current density exceeds the standard from the calibrated area. The designed layout is optimized and rectified, but as the shape of the integrated circuit layout becomes more and more complex, the original calibration method is no longer effective. Specifically, there are a large number of curved strip layout polygons. If the current density on this polygon According to the traditional calibration method, the over-standard rectangular area including the entire strip layout polygon is included. This rectangular area also contains a large number of layout polygons that do not exceed the standard. Therefore, this calibration is basically invalid and cannot be obtained from Accurately obtain useful information in the marked area

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