A method and system for calibrating an area where the current density of an integrated circuit layout exceeds the standard

Abstract

This application discloses a method and system for calibrating the area where the current density exceeds the standard in the layout of an integrated circuit, which belongs to the technical field of electromagnetic field analysis of integrated circuits, including: performing grid division on the layout of the integrated circuit, and using the numerical calculation method of the electromagnetic field to calculate the grid in each layer of the layout. The current density of grid cells; based on the current density of grid cells in each layer layout, identify the grid cells whose current density exceeds the standard; based on the identified grid cells whose current density exceeds the standard, use the neighbor search method to identify connected grid cells , form a connected grid unit area, and for each connected grid unit area, set the edge corresponding to the grid unit without neighbor grid units as the boundary of the connected grid unit area. This application solves the problem that when the shape of the integrated circuit layout is complex, the traditional current density calibration method is no longer effective, and the area where the current density exceeds the standard cannot be accurately calibrated, which is helpful for the layout optimization and rectification of large-scale integrated circuits.

Description

technical field [0001] The application belongs to the technical field of integrated circuit electromagnetic field analysis, in particular to an integrated circuit layout current density exceeding standard area calibration method and system. Background technology [0002] With the development of communication technology, the research and development of VLSI has been gradually carried out. In order to improve the performance of electronic equipment, reduce volume and reduce cost, the current production status is to integrate transistors with other components and circuits on a small semiconductor substrate. In order to achieve more functions, at present, VLSI has several to hundreds of layers. The structure of each layer is extremely complex, and tens of millions or even hundreds of millions of transistors are integrated, and all of them have the latest nanoscale multi-scale structure from centimeter level to current level. Such a complex structure also brings difficulties to its el...

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Problems solved by technology

[0005] At present, the calibration of the area where the current density exceeds the standard on the integrated circuit layout is usually a rectangular area calibration. This calibration method is effective for the layout shape with a simple structure in the early stage, and can quickly identify the position where the current density exceeds the standard from the calibrated area. The designed layout is optimized and rectified, but as the shape of the integrated circuit layout becomes more and more complex, the original calibration method is no longer effective. Specifically, there are a large number of curved strip layout polygons. If the current density on this polygon According to the traditional calibration method, the over-standard rectangular area including the entire strip layout polygon is included. This rectangular area also contains a large number of layout polygons that do not exceed the standard. Therefore, this calibration is basically invalid and cannot be obtained from Accurately obtain useful information in the marked area

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