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A heap memory management method and device for a shared memory coprocessor

A coprocessor and shared memory technology, which is applied in the computer field, can solve the problems that the coprocessor does not have dynamic memory management capabilities, can only recognize physical addresses, and cannot meet the needs of the coprocessor side to use dynamic memory, etc., to achieve The effect of the ability to dynamically apply and release memory

Active Publication Date: 2022-05-24
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing shared memory coprocessor cannot run the operating system, does not have the ability to convert virtual and real addresses, and can only recognize physical addresses
Therefore, the coprocessor itself does not have dynamic memory management capabilities, and cannot meet the demand for using dynamic memory on the coprocessor side.

Method used

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  • A heap memory management method and device for a shared memory coprocessor
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  • A heap memory management method and device for a shared memory coprocessor

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Embodiment Construction

[0050] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0051] The heap memory management method for a shared memory coprocessor provided by the present application can be applied to the following application environments. The shared memory coprocessor is connected to the CPU through a high-speed bus in the chip, and can realize shared memory with the CPU. The present invention executes a heap memory management method oriented to the shared memory coprocessor through the terminal. , apply for a large continuous memory space in advance, and transfer the physical address of the space to the coprocessor-side program. On the c...

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Abstract

The present application relates to a heap memory management method and device for a shared memory coprocessor. The method includes: before executing the co-processing terminal program, applying for a larger continuous heap memory space through the first interface function, converting the virtual address of the applied heap memory space into a physical address, and passing the physical address to the co-processing The coprocessor-side program organizes the requested heap memory space into an available linked list and an allocated linked list; when the coprocessor-side program applies for memory usage, the second interface function starts from the head of the available linked list to find the first block of available memory Allocation, and add the newly allocated memory to the end of the linked list of the allocated linked list; during the execution of the coprocessor side program, release the coprocessor side heap memory space through the third interface function, and add the newly released memory to the available linked list; After the coprocessor end program is executed, the coprocessor heap memory space is cleared according to the virtual address through the fourth interface function.

Description

technical field [0001] The present application relates to the field of computer technology, and in particular, to a heap memory management method and device for a shared memory coprocessor. Background technique [0002] Heterogeneous computing has been continuously developed in the field of high-performance computing due to its high performance and high energy efficiency, and more and more coprocessors have emerged, such as GPU (Graphics Processing Unit, graphics processing unit), FPGA (Field-programmable Gate) Array, Field Programmable Logic Gate Array) and so on. Usually the coprocessor is connected to the host-side CPU (Central Processing Unit, central processing unit) in the form of PCIe (Peripheral Component Interconnect Express) peripherals, and has its own independent storage unit, which cannot be directly connected to the CPU. Shared memory is a separate memory coprocessor. The separate memory coprocessor needs to explicitly transfer data between the memory and the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50G06F15/167
CPCG06F9/5016G06F9/5022G06F15/167
Inventor 张昂廖湘科崔英博杨灿群黄春唐滔彭林夏泽宇郭逸飞
Owner NAT UNIV OF DEFENSE TECH
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