Architecture optimization method and device for loop body

Abstract

The invention provides an architecture optimization method and device for a loop body, and the method comprises the steps: judging whether a current instruction is a short loop body instruction, and if yes, caching the current instruction in a short loop body cache; table look-up is conducted on the PC value of the current instruction, if effective records matched exist in the table, it is determined that the current instruction is a conditional branch instruction for controlling the loop body, and subsequent instructions are prefetched from the corresponding jumppc position in the table. According to the architecture optimization method and device for the loop body, provided by the invention, the branch instruction of the short loop body can be taken out more efficiently and quickly with lower power consumption, and the probability of cavitation bubbles in an assembly line is reduced, so that the problem of low kernel performance caused by slow instruction taking of the assembly line is avoided as much as possible; according to the method, more accurate loop body prediction is realized, conditional branch instructions for loop body control can be rapidly detected, the frequency of assembly line scouring is reduced, and the performance of a processor is improved.

Description

technical field [0001] The present disclosure relates to the field of computer technology, and in particular to a method and device for optimizing the architecture of a loop body. Background technique [0002] In a program, there are usually a large number of loop statements. In C code, it is generally embodied as a statement in the form of for, while, do...while. The content in the loop body needs to be fetched and executed repeatedly. Just because the contents of the registers are different, the execution results are different. [0003] First of all, in terms of branch prediction, for the branch prediction behavior of the loop body, the academic community has proposed a strategy of "jump backward, not jump forward". The backward jump here means that the jump target address is smaller than the current address. Jumping forward means that the jump target address is greater than the current address. But there is no mention of how the loop body is detected. The conditional...

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Problems solved by technology

[0004] On the other hand, front-end instruction fetching generally focuses on how to quickly access icache fetching of instructions and instruction prefetching, which is useful for reducing the number of accesses to the cache for short loops (the number of instructions in the loop is small) to save power consumption and speed up the execution of instructions in short loops. Taken out, this type of research has received little attention

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