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Burr eliminating circuit

A technology of circuits and latches, applied in the field of circuits, can solve problems such as introducing burrs, and achieve the effect of eliminating burrs and avoiding combinational logic loops

Active Publication Date: 2021-11-19
芯华章科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This may introduce glitch problems

Method used

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  • Burr eliminating circuit
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Embodiment Construction

[0013] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0014] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connectio...

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Abstract

The invention provides a burr eliminating circuit, which comprises a first latch, a second latch, a selector and a third latch, and is characterized in that the selector comprises a first input end, a second input end, a gating input end and a gating output end, wherein the first latch comprises a first data input end for receiving data, a first clock input end for receiving a first clock, and a first data output end connected to the first input end; the second latch comprises a second data input end connected with the gating output end, a second clock input end used for receiving the first clock, and a second data output end connected to the second input end; the third latch comprises a third data input end used for receiving the second clock, a third clock input end used for receiving the first clock and a third data output end connected to a phase inverter, the phase inverter and the second clock serve as input of an AND gate unit, and the output end of the AND gate unit is connected to the gating input end.

Description

technical field [0001] The present disclosure relates to the field of circuits, in particular to a circuit for removing burrs. Background technique [0002] A common chip design includes multiple modules, and each module may be in a different clock domain. That is, multiple modules may be driven by user clock signals of different frequencies. When performing hardware simulation on chip design, the simulation system usually uses a system clock with a faster frequency to replace these different user clocks. This may introduce glitch problems. Contents of the invention [0003] In view of this, the present disclosure proposes a circuit for eliminating glitches. [0004] The present disclosure provides a circuit for eliminating burrs, including: a first latch, a second latch, a selector, and a third latch, wherein the selector includes a first input terminal, a second input terminal , a strobe input terminal and a strobe output terminal, the first latch includes a first da...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/1252
CPCH03K5/1252
Inventor 常清云徐欣
Owner 芯华章科技股份有限公司
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