Comprehensive CPU model

Abstract

The invention discloses a Comprehensive CPU model; the CPU model is provided with a plurality of bus interfaces, and each bus interface has own ID. The CPU model comprises an instruction acquisition module, an instruction analysis module, a data comparison module, an interface arbitration routing module and a bus protocol generation module. The instruction acquisition module is used for acquiring an instruction required by model operation and providing the instruction to the instruction analysis module; the instruction analysis module parses the compiled instruction into a binary system which can be identified by a CPU so as to achieve the purpose of distinguishing an instruction function, and then transmits the parsed instruction to the data comparison module; the data comparison module is used for comparing an instruction execution result with the received instruction so as to judge whether the instruction is correctly executed or not; the interface arbitration routing module determines a sending bus port according to the content of the instruction; and the bus protocol generation module sends the received instruction or data to a bus interface according to a bus protocol format.

Description

technical field [0001] The invention relates to a synthesizable CPU model, which is used for logic function verification between the CPU and the bus. Background technique [0002] With the continuous development of integrated circuits, the scale of system design is getting larger and larger, and the division of modules is becoming more and more complicated. As the core CPU for scheduling system work, it is becoming more and more important. Generally, the CPU is an important part of the system, and the authorized IP is mostly used, and the flexibility and convenience of use are limited. In the entire ASIC design process, it is necessary to configure CPU parameters in the early stage, integrate the CPU into the system, and perform RTL simulation. In the later stage, it is necessary to perform FPGA synthesis and board debugging. After a series of behaviors, the entire system can be scheduled through the CPU to observe whether the behavior of the entire system meets expectation...

AI Technical Summary

Problems solved by technology

However, if you only verify the logic functions outside the CPU, this will bring huge time and labor costs

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