Hierarchical SoC test scheme based on IEEE1149 and IEEE1500 standards

Abstract

The invention discloses a hierarchical SoC test scheme based on IEEE1149 and IEEE1500 standards, and relates to the field of SoC chip testing. The IEEE1500 standard protocol is used for independently testing a single embedded kernel in the SoC, and an IP kernel test structure is standardized by defining a kernel test interface between the embedded kernel and the system, so that test reuse of the kernel is facilitated through a kernel access mechanism; meanwhile, test and isolation of the kernel and switching between partition test blocks are effectively completed, and the purpose of completely testing the SoC is achieved; according to the invention, by improving a peripheral circuit integrated by an IP kernel, parallel and synchronous testing of kernels and outer cores in the hierarchical SoC is realized, and finally, the purpose of reducing the testing time is achieved; and a flexible and high-efficiency design scheme can be provided for a large SoC product.

Description

technical field [0001] The invention relates to the field of SoC chip testing, in particular to a hierarchical SoC testing scheme based on IEEE1149 and IEEE1500 standards. Background technique [0002] When integrated circuits (Integrated Circuit, referred to as IC) enter the era of VLSI, testability design is an important link in circuit and chip design. control and observability) hardware logic, which makes the chip easy to test and greatly saves the cost of chip testing. [0003] With the increase of integration and design complexity of System-on-a-chip (SoC for short), chip testing has encountered great challenges. On the one hand, IP multiplexing technology can speed up the SoC design process, improve system integration, and make a single chip more functional and more powerful; on the other hand, with the increase in the number of integrated IP cores on a single chip, SoC design complexity and The sharp increase in circuit scale has caused SoC testing to face huge cha...

AI Technical Summary

Problems solved by technology

Different suppliers will provide a variety of IP cores according to different test types and test requirements, but the detailed information inside the IP core is difficult to obtain due to intellectual property rights.

Usually, the data transfer speed between embedded cores is faster than the data transfer speed from chip pins to IP cores, so boundary scan alone cannot completely solve the testing problem of embedded cores in SoC

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