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Verification method, device and equipment for algorithm module in chip and readable storage medium

A technology of algorithm module and verification method, which is applied in the directions of calculation, instrumentation, error detection/correction, etc., can solve the problems of inability to quickly and effectively locate the error position and inconvenient use, so as to ensure timing consistency, reduce workload, and improve verification efficiency effect

Active Publication Date: 2021-08-24
山东云海国创云计算装备产业创新中心有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Calling the C interface function needs to be called at a specific moment, and it needs to be called multiple times, which is inconvenient to use. When the chip algorithm module fails to pass the verification, it is impossible to quickly and effectively locate the error position

Method used

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  • Verification method, device and equipment for algorithm module in chip and readable storage medium
  • Verification method, device and equipment for algorithm module in chip and readable storage medium
  • Verification method, device and equipment for algorithm module in chip and readable storage medium

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Embodiment 1

[0073] see figure 1 , figure 1 It is an implementation flowchart of a method for verifying an algorithm module in a chip in an embodiment of the present invention, and the method may include the following steps:

[0074] S101: Analyzing the received algorithm module verification request to obtain a target algorithm module to be verified.

[0075] When the algorithm module in the chip needs to be verified, an algorithm module verification request is sent to the pre-built chip algorithm module verification platform. The algorithm module verification request can include the target algorithm module to be verified, the chip information to which the target algorithm module belongs, etc. The chip algorithm module verification platform receives the algorithm module verification request, and analyzes the received algorithm module verification request to obtain the target algorithm module to be verified.

[0076] S102: Call the target SystemC reference model corresponding to the pre-b...

Embodiment 2

[0089] see figure 2 , figure 2 It is another implementation flowchart of the verification method of the algorithm module in the chip in the embodiment of the present invention, and the method may include the following steps:

[0090] S201: Analyzing the received algorithm module verification request to obtain a target algorithm module to be verified.

[0091] S202: Call the target SystemC reference model corresponding to the pre-built target algorithm module.

[0092] see image 3 It is a structural block diagram of a SystemC reference model corresponding to a compression algorithm module in an embodiment of the present invention. When the target algorithm module is a compression algorithm module, the compression algorithm module searches for repeated parts in the input original text and replaces these repeated parts with a specific code, thereby replacing a long original text with a shorter code , so as to realize the compression of the input. The SystemC reference mod...

Embodiment 3

[0169] Corresponding to the above method embodiment, the present invention also provides a verification device for the algorithm module in the chip, the verification device for the algorithm module in the chip described below and the verification device method for the algorithm module in the chip described above can refer to each other .

[0170] see Figure 6 , Figure 6 It is a structural block diagram of a verification device for an algorithm module in a chip in an embodiment of the present invention, and the device may include:

[0171] The request parsing unit 61 is configured to parse the received algorithm module verification request to obtain the target algorithm module to be verified;

[0172] Model calling unit 62, used to call the target SystemC reference model corresponding to the pre-built target algorithm module;

[0173] The use case input unit 63 is used to obtain each test case corresponding to the target algorithm module through a preset input agent, and i...

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Abstract

The invention discloses a verification method for an algorithm module in a chip, and the method comprises the steps: carrying out the analysis of an algorithm module verification request, and obtaining a to-be-verified target algorithm module; calling a target SystemC reference model corresponding to the target algorithm module; obtaining each test case corresponding to the target algorithm module through a preset input agent, and respectively inputting each test case into the target SystemC reference model and the target algorithm module according to a preset time sequence; utilizing an output agent to respectively obtain each level of output of the target SystemC reference model and the target algorithm module; and performing corresponding comparison on each level of output to obtain a verification result of the target algorithm module. According to the method, the time sequence consistency of the target SystemC reference model and the target algorithm module is ensured, the workload is greatly reduced, and the verification efficiency is improved. The invention further discloses a device, equipment and a storage medium, which have corresponding technical effects.

Description

technical field [0001] The invention relates to the technical field of computer applications, in particular to a verification method, device, equipment and computer-readable storage medium for an algorithm module in a chip. Background technique [0002] With the continuous development of the system on chip (System on Chip, SOC) technology, the complexity of the design continues to increase, which greatly increases the complexity of the SOC verification, and the verification accounts for a large proportion of the entire SOC development process time. Especially the SOC of the algorithm class contains complex algorithms inside, which makes the design and verification of the chip quite complicated. [0003] The verification of the algorithm modules in the chip requires a corresponding algorithm reference model. The traditional reference model is generally implemented in C language or C++ language. C, C++ and other high-level programming languages ​​have high abstraction ability,...

Claims

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Application Information

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IPC IPC(8): G06F11/36
CPCG06F11/3688G06F11/3692G06F11/3676G06F11/3684
Inventor 李靖蕙邵海波祁鹏展
Owner 山东云海国创云计算装备产业创新中心有限公司
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