Instruction caching method and device

Abstract

The invention relates to an instruction caching method, which comprises the following steps: responding to an access request signal, and sending out a first reading request; obtaining label data and effective indication data according to the first reading request, wherein the label data and the effective indication data are stored in a register block; judging whether target instruction data exists or not according to the label data, the effective indication data and an access address signal; and if the target instruction data exists, returning the target instruction data to the CPU. According to the instruction caching method, the tag data and the effective indication data are obtained from the register block, the TAG_SRAM originally used for storing the tag data in the cache is replaced, and the problem of high power consumption when a CPU reads a plurality of SRAMs at the same time is solved. Meanwhile, the reading speed between the CPU and the register block is higher than the reading speed between the CPU and the SRAM, so that the instruction caching method can also improve the CPU instruction reading efficiency.

Description

technical field [0001] The invention relates to the field of chip circuit design, in particular to an instruction cache method and device. Background technique [0002] Due to the limitation of memory read speed, the mismatch between memory speed and CPU speed becomes a bottleneck that limits system performance. Based on the time and space limitations of the CPU access program, a small-capacity instruction cache (Instruction Cache, ICACHE) can be used to make up the difference between the CPU and the speed, thereby improving the overall performance of the system. Cache (cache) is one of the important foundations for the high performance of all modern computers. It is generally composed of SRAM, the speed is very fast, and it can perform high-speed data exchange with the CPU. Normally, the CPU first looks for the required data in the cache, and when there is no data required by the CPU in the cache, the CPU accesses it again. When the CPU finds the target data in the cache...

AI Technical Summary

Problems solved by technology

[0008] Based on this, it is necessary to provide a new instruction cache method and device for the problem that the traditional ICACHE design needs to read multiple SRAMs at the same time, resulting in increased CPU power consumption.

Images