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SystemVerilog coverage set generation method and device

A technology covering sets and excel, applied in special data processing applications, instruments, electrical and digital data processing, etc., can solve problems such as low efficiency and large workload, and achieve the effect of improving efficiency, avoiding low efficiency and avoiding large workload.

Active Publication Date: 2021-07-23
四川微巨芯科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

During project execution, if the module verification is very complicated, there will be a large amount of writing of the corresponding functional coverage set, and manual writing of the coverage set is a lot of work and inefficient

Method used

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  • SystemVerilog coverage set generation method and device
  • SystemVerilog coverage set generation method and device
  • SystemVerilog coverage set generation method and device

Examples

Experimental program
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Embodiment

[0043] figure 1 A flowchart of a SYSTEMVERILOG overlay set is provided by an embodiment of the present invention, which can be performed by the Systemverilog overlay set generating device provided by the embodiment of the present invention. refer to figure 1 This method can include the following steps:

[0044] S101, based on preset, written to the collection of functional test points in the Excel document according to the preset rules;

[0045] It should be noted that in the present application providing, verify that workers need to quantify the function point in the Excel documentation to be quantified by: functional test points. Of course, in the process of writing the relevant information of the function test point, you need to follow the pre-set rules. Because the syntax is a single, and the syntax is compared, and the law can be followed, the verification engineer can make the verification engineer fill in the function test point that needs to be collected by the friendly i...

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Abstract

The invention relates to a SystemVerilog coverage set generation method and device. The method comprises the following steps: writing related information of collected function test points into an Excel document according to a preset rule based on a preset rule; and generating a coverage set based on the Excel document by using a preset script. By the adoption of the technical scheme, a verification worker only needs to quantify the function points in the Excel file through a more friendly input interface, and then the Perl automatically generates the coverage set based on the file so as to improve efficiency. And the problems of large workload and low efficiency of manual writing of the coverage set are avoided.

Description

Technical field [0001] The present invention relates to an integrated circuit code level verification related to the technical field, and more particularly to a systemverilog coverage formation method and apparatus. Background technique [0002] Random integrated circuits are increasing, and Verilog RTL code level functional verification is increasing, and the random verification method based on systemverilog syntax is also promoted, and the completeness of functional verification under random verification methods is made by the overlay set. ensure. During the project execution, if a complicated module verifies, there will be a large number of copies of the corresponding function override set, and the manual writing overlay set is very efficient. Inventive content [0003] In view of this, there is provided a systemverilog cover integrated method and device to solve problems in the background. [0004] The present invention adopts the following technical solution: [0005] In th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/367
CPCG06F30/367
Inventor 朱琳琳刘小波杜世淼
Owner 四川微巨芯科技有限公司
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