A chip design optimization system and method based on dynamic unbalanced clock

Abstract

The invention proposes a chip design optimization system and method based on a dynamic unbalanced clock. In the synthesis stage of the design, it analyzes the timing path of the design, analyzes and dynamically adjusts the clock delay of the sequential unit according to the current timing results, and transfers the clock delay results to the subsequent steps of the chip design and implementation process, so that when the clock tree is synthesized , synthesize an unbalanced clock tree structure according to the requirements. During the synthesis and placement and routing phases of the chip design implementation process, the delay of the entire leaf node clock network is dynamically adjusted to achieve the purpose of quickly converging timing. Due to the use of a dynamic unbalanced clock network, the timing path of the chip design has more timing margins, so that the chip implementation tool can better optimize the timing of the entire design, and the timing tight path no longer needs more complicated Optimization, thereby reducing the area of ​​the entire design, reducing power consumption, increasing the achievable clock speed of the design, and improving the performance of the design.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a chip design optimization system and method based on a dynamic unbalanced clock. Background technique [0002] The integrated circuit design and implementation process includes a synthesis stage and a layout and routing stage. In the synthesis stage, in the traditional process, the clock is ideal, and the delay from the clock source to different registers is the same, only from the timing constraints of the design. Use the clock uncertainty (Clock Uncertainty) to be constrained. This kind of constraint is relatively arbitrary, and it is difficult to meet the design constraint requirements for some timing paths with relatively tight timing requirements. However, in the implementation process, if such a timing path has a timing margin in the forward timing path or the backward timing path, the timing path can be made Meet the final design requirements. T...

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Problems solved by technology

[0003] Aiming at the shortage of balanced clock tree in the existing chip design and implementation process, the present invention proposes a chip design optimization system and method based on dynamic unbalanced clocks, so as to improve the running speed of the chip and reduce the power consumption and area of ​​the chip

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