GPU (Graphics Processing Unit) chip element output control-oriented TLM (Transport Length Modulation) device based on SystemC and operation method

Abstract

The invention relates to the technical field of computer hardware modeling, in particular to a GPU chip element output control-oriented TLM device based on SystemC and an operation method. The TLM device comprises a PCIE bus unit, a state parameter management unit, a fragment task assembly unit, a unified dyeing unit, a fragment output control unit, a register unit and a fragment processing unit.The system further comprises a plurality of transaction-level interfaces used for connecting all the units. The method comprises the steps that 1, an initialization module judges the states of simplemode chip element attribute data FIFO and complex mode chip element attribute data FIFO; 2, the simple-mode chip element assembly module executes chip element output assembly in a simple mode; and 3,the complex mode chip element assembly module executes chip element output assembly in a complex mode. According to the SystemC-based GPU chip element output control-oriented TLM device and the operation method, the problems of RTL simulation result model ratio and function verification of the GPU chip element output control-oriented TLM device are solved, and the simulation speed is increased.

Description

technical field [0001] The invention belongs to the technical field of computer hardware modeling, and relates to a GPU fragment output control TLM device, in particular to a SystemC-oriented GPU fragment output control TLM device and an operation method. Background technique [0002] With the continuous increase of graphics applications, the early solution of graphics rendering by CPU alone has been difficult to meet the graphics processing needs of performance and technology growth, and the graphics processing unit (Graphic Processing Unit, GPU) came into being. Since the release of the first GPU product by Nvidia in 1999, the development of GPU technology has mainly gone through the fixed-function pipeline stage, the stage of separating the dyer architecture, and the stage of unified dyer architecture. Rendering gradually extends to the field of general computing. The high-speed, parallel features and flexible programmability of the GPU pipeline provide a good operating ...

AI Technical Summary

Problems solved by technology

Traditional hardware design starts with functional specifications and is refined step by step to the RTL level to enter the simulation and verification stage. Verification has become the bottleneck of chip design and development.

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