DAC capacitor array, SAR type analog-to-digital converter and analog-to-digital conversion method

Abstract

The invention relates to the technical field of integrated circuits, and provides a DAC capacitor array which splits an existing first capacitor array and an existing second capacitor array to form afirst high-section capacitor array, a first low-section capacitor array, a second high-section capacitor array and a second low-section capacitor array. The weight of each capacitor in the first high-section capacitor array and the weight of each capacitor in the first low-section capacitor array meet a preset proportional relation; a first connecting switch is arranged between the upper pole plate of the first high-section capacitor array and the upper pole plate of the first low-section capacitor array; the weight of each capacitor in the second high-section capacitor array and the weight ofeach capacitor in the second low-section capacitor array meet the preset proportional relation; and a second connecting switch is arranged between the upper pole plate of the second high-section capacitor array and the upper pole plate of the second low-section capacitor array. According to the technical scheme provided by the invention, the establishment time of the capacitor voltage of the SARtype analog-to-digital converter in the quantization process can be greatly shortened, and the quantization speed of the SAR type analog-to-digital converter is effectively improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a DAC capacitor array, a SAR analog-to-digital converter and an analog-to-digital conversion method. Background technique [0002] The most important module in a SAR-type analog-to-digital converter (Successive Approximation ADC, SAR ADC) is a digital-to-analog converter (Digital Analog Converter, DAC), and the most commonly used architecture of the DAC is a capacitor array. Such as figure 1 As shown, the common connection of the upper plate of each capacitor in the capacitor array is used as the output, and the lower plate on the other side is connected to different voltages through the digital control module, so that the corresponding analog signal is obtained on the upper plate to realize the digital output. Modular conversion. exist figure 1 Among them, end a is the upper plate of the capacitor, and end b is the lower plate of the capacitor. Such as figure 2...

AI Technical Summary

Problems solved by technology

When the capacitor is flipped, the voltage of the lower plate changes. Although the total charge of the common upper plate remains unchanged, it will be redistributed among the capacitors, which results in the charging and discharging of the capacitor. Because there is a certain amount of charge on the lower plate switch of the capacitor Therefore, it takes a certain amount of time until the capacitor voltage is established after the capacitor is flipped (referring to the completion of charging and discharging of the capacitor, the entire DAC reaches a stable state, and the voltage of the upper plate of the capacitor is stable), and the next step can only be performed after the voltage of the upper plate is stable. rounds of quantization, so this is the main reason for limiting the speed of the ADC

In high-precision applications, the capacitance of the high-level capacitor is large, and the large RC time constant makes the establishment of the capacitor voltage take a long time. Since each comparison in the quantization process must wait for the capacitor voltage to be established, the voltage of the high-level capacitor The settling time limits the quantization speed of the ADC

[0005] In order to solve the above problems, one of the most common methods at present is to increase the size of the control switch to reduce the on-resistance of the control switch so that it has a stronger driving capability. However, this method does not directly solve the high capacitor voltage settling time. The long problem, and this method creates new difficulties for the reference voltage generation circuit; another method is to reduce the unit capacitance so that the weight / capacitance value of the high-level capacitor is correspondingly reduced, but it is affected by noise and limited by the manufacturing process The unit capacitance cannot be reduced indefinitely. Using a smaller unit capacitance will inevitably reduce the accuracy of the analog-to-digital converter, which may require an additional calibration circuit to solve the problem. The cost is high and the improvement effect on the capacitor voltage settling time is limited.

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