Method for debugging main computing core by utilizing on-chip co-computing core
A technology for computing cores and debugging hosts, applied in general-purpose stored program computers, computing, computers, etc., and can solve problems such as low efficiency
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[0014] As the co-computing core that completes some auxiliary functions, it has the ability to control the on-chip peripheral resources, control the Ethernet interface, UART interface or other communication interfaces to communicate with the host computer. Internally, the co-computing core connects each peripheral device and each main computing core through an internal bus; externally, it controls the peripheral devices communicating with the upper computer, such as Ethernet interface, UART interface, etc., such as figure 1 shown. The present invention designs a method for debugging the main computing core by utilizing the on-chip co-computing core based on the characteristics of the co-computing core itself.
[0015] The co-computing core communicates with the debugging host through a communication interface used solely for debugging, analyzes the debugging commands sent by the debugging host, and converts them into operation sequences on the internal bus of the chip, and con...
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