Circuit for reducing leakage current of SRAM storage array and control method

Abstract

The invention discloses a circuit for reducing leakage current of an SRAM (Static Random Access Memory) storage array and a control method. The circuit comprises a storage array power supply voltage control module, a storage array ground terminal voltage control module and the storage array; the voltage of the power supply end and the voltage of the ground end of the storage array are controlled through the storage array power supply voltage control module and the storage array ground end control module, and the actual data holding voltage of the storage unit can be reduced, so that the electric leakage power consumption of the SRAM in a data holding state is reduced. The function of adjusting the data maintaining voltage value of the storage unit is realized by controlling different adjusting signals so as to meet different design requirements. According to the invention, the leakage current of the storage array of the SRAM in the number holding state can be effectively reduced, and in a storage system realized by the SRAM, a low-power-consumption scheme that the necessary SRAM holds data with low electric leakage overhead and the rest SRAMs completely turn off a power supply canbe realized.

Description

technical field [0001] The invention belongs to the technical field of SRAM, and in particular relates to a circuit and a control method for reducing the leakage current of an SRAM storage array. Background technique [0002] With the continuous development of IoT technology, the demand for high-energy-efficiency microcontrollers used in IoT sensor nodes is growing rapidly. Due to the characteristics of battery power supply, the design of microcontrollers with low power consumption becomes the key. The typical working characteristic of microcontrollers applied to the Internet of Things technology is that they are in sleep mode for a long time, so it is particularly important to reduce the leakage power consumption of microcontrollers in sleep mode, and the static leakage power consumption of SRAM is the main source of power consumption. [0003] In the prior art, the peripheral logic circuits of the SRAM usually use power gating to reduce the leakage current in the dormant s...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, the peripheral logic circuits of SRAM usually use power gating to reduce the leakage current in the sleep state, and the storage array only limits the leakage power consumption by turning off the power gating when the data does not need to be kept.

For some SRAMs that need to save data, the storage array is still in the normal power supply state, resulting in a large leakage power consumption of the storage array, which limits the further improvement of the energy efficiency of the microcontroller

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