Intrinsic linear phase interpolator

Abstract

The invention provides an intrinsic linear phase interpolator. The intrinsic linear phase interpolator comprises a phase interpolation module, a first constant current source module and a second constant current source module. The phase interpolation module comprises a first capacitor bank and a second capacitor bank, the first constant current source module is used for charging or discharging thefirst capacitor bank by adopting a constant current, and the second constant current source module is used for charging or discharging the second capacitor bank by adopting a constant current. In theintrinsic linear phase interpolator,the intrinsic linear phase interpolator comprises thefirst constant current source module and thesecond constant current source module. The first constant currentsource module is used for charging or discharging the first capacitor bank by adopting the constant current; and the second constant current source module is used for charging or discharging the second capacitor bank by adopting the constant current, so that the current change of the first capacitor bank and the second capacitor bank in the charging and discharging process on an intrinsic or mathematical expression is linear, the phase cause is optimized, and the introduction of stray is reduced.

Description

technical field [0001] The invention relates to the technical field of phase-locked loops, in particular to an intrinsic linear phase interpolator. Background technique [0002] The quantization noise introduced by the delta-sigma modulator (Sigma-Delta Modulator, SDM) in the fractional-N PLL will bring jitter to the output clock. Among them, the fractional divider (Fractional Divider) implemented by the intrinsic linear phase interpolator (Phase interpolator) can effectively reduce the quantization noise, but in the process of charging and discharging the capacitor of the intrinsic linear phase interpolator, the nonlinear change of the current magnitude will be degrade phase noise or introduce spurs. [0003] Therefore, it is necessary to provide a novel intrinsic linear phase interpolator to solve the above-mentioned problems in the prior art. Contents of the invention [0004] The purpose of the present invention is to provide an intrinsic linear phase interpolator, w...

AI Technical Summary

Problems solved by technology

[0002] The quantization noise introduced by the Sigma-Delta Modulator (SDM) in the Fractional-N PLL will bring jitter to the output clock

Among them, the fractional divider (Fractional Divider) implemented by the intrinsic linear phase interpolator (Phase interpolator) can effectively reduce the quantization noise, but in the process of charging and discharging the capacitor of the intrinsic linear phase interpolator, the nonlinear change of the current magnitude will be degrade phase noise or introduce spurs

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