3D NAND memory and manufacturing method thereof

Abstract

The invention provides a 3D NAND memory and a manufacturing method thereof. According to the method, a stacked structure comprising a bottom sacrificial layer, sacrificial layers and insulating layersis formed on a substrate, the sacrificial layers and the insulating layers are alternately stacked on the bottom sacrificial layer, the bottom sacrificial layer is replaced with a source electrode layer, oxidation treatment is conducted on the source electrode layer, a first isolation layer is formed on the surface of the source electrode layer, and the function of selecting gate oxide on the back is achieved. The method facilitates control over thickness of the first isolation layer and improves the uniformity of the first isolation layer, so that uniform inversion of the source electrode layer is facilitated, and an electronic channel is ensured in read-write operation of the memory. The problems in the thickness and uniformity of the source electrode layer caused by the thickness problem of the back selection gate oxide layer are solved, and the continuity of a P-type trap and supply of holes in the erasing process can be realized. The source electrode layer is formed in the channel structure in the stacking direction at the same time, the contact area of the source electrode layer and the channel layer is increased, and electrical connection between the source electrode layerand the channel layer is enhanced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof. Background technique [0002] As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and lower cost per bit are increasingly favored. 3D memory is a technology for stacking data units. Currently, more than 32 layers, or even 72, 96, 128 or more layers of data units can be stacked. As the number of stacked layers increases, the lead-out of the memory structure that runs through the stacked structure faces increasing challenges. [0003] The traditional method of realizing the communication between the channel structure and the substrate usually faces the problem of defects in the uniformity and continuity of the epitaxial structure, or the difficulty in controlling the thickness ...

AI Technical Summary

Problems solved by technology

[0003] The traditional method of realizing the communication between the channel structure and the substrate usually faces the problem of the uniformity and continuity of the epitaxial structure, or the difficulty of controlling the thickness of the back selection gate oxide.

In the multi-layer trench hole process, it will also face the problem of increased etching difficulty of the stacked structure

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