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A Method for Realizing Data Consistency Based on Advance Update

An implementation method and consistent technology, which is applied in the fields of electrical digital data processing, instruments, calculations, etc., can solve the problems of large read and write delays of the main memory, take a long time, and cannot fully utilize the performance of DMA, etc., so as to alleviate the delay Problems, Effects of Efficiency Improvement

Active Publication Date: 2022-04-29
JIANGNAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

According to the large amount of data transferred by DMA at one time and the large read and write delay of the main memory, the cache refresh operation before DMA transfer takes a long time, and the performance of DMA cannot be fully utilized.

Method used

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  • A Method for Realizing Data Consistency Based on Advance Update
  • A Method for Realizing Data Consistency Based on Advance Update
  • A Method for Realizing Data Consistency Based on Advance Update

Examples

Experimental program
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Effect test

Embodiment 1

[0049] This embodiment provides a method for implementing data consistency based on early update, which is applied to a multi-core processor system. During the implementation process, a counter is added for each L1 DCache and the Cacheline of other levels of Cache to record the number of dirty data copies. Cacheline access status, write the copy containing dirty data back to the main memory in advance, effectively alleviate the delay problem caused by the Cache refresh operation before DMA transfer data, and improve the efficiency of the DMA transfer system.

[0050] The maximum value that the counter that the present invention increases can record is the Cacheline quantity N of current Cache, promptly the bit width of counter is [log 2 N-1,0]. A multi-core processor system contains at least two CPUs,

[0051] see figure 1 , the method includes:

[0052] Step 1. The first CPU requests to access a certain data copy, and the first CPU is any CPU in the multi-core processor sy...

Embodiment 2

[0070] This embodiment provides a description of the practical application of the method for realizing data consistency based on early update described in Embodiment 1, see figure 2 ,details as follows:

[0071] In this embodiment, the hardware device includes a multi-core processor system, and the multi-core processor system includes CPU0, CPU1, a second-level shared high-speed cache (L2 Cache), a bus (Bus), a main memory (Mem) and an interconnection structure. Among them, each CPU adopts Haval structure, including a 32kB instruction cache (ICache) and data cache (DCache).

[0072] The L1 DCache adopts a 4-way set associative organizational structure, the number of groups is 64, and the cacheline size is 128 bytes. Therefore, the maximum value N that can be recorded by the counter corresponding to the dirty cacheline of the L1 DCache is 256.

[0073] This embodiment is based on the write-back method and the write invalidation strategy, and uses the MSI protocol (Modified Sh...

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Abstract

The invention discloses a data consistency realization method based on advance update, which belongs to the technical field of integrated circuits. The method includes adding a counter for each L1 DCache and Cachelines of other levels of Cache to record the access conditions of the Cachelines containing dirty data copies, thereby advancing the data copies containing dirty data in the Cache when the memory is free Update to the next-level memory instead of refreshing the Cache before DMA transfers data, thereby alleviating the delay problem caused by the Cache refresh operation before DMA transfers data, fully mobilizing the memory, and improving the efficiency of the DMA transfer system.

Description

technical field [0001] The invention relates to a method for implementing data consistency based on advance update, and belongs to the technical field of integrated circuits. Background technique [0002] At present, mainstream processors mostly use a hierarchical storage system, that is, a multi-level Cache (high-speed cache memory) is added between the processor and the main memory (hereinafter referred to as "main memory") to make up for the performance gap between the CPU and the main memory. . [0003] Cache stores part of the data copy of the main memory, and usually adopts two writing strategies of write-back method or write-through method to maintain data consistency of multi-level cache. The former only writes the copy of the dirty data back to the main memory when the dirty Cacheline is replaced or invalid. This strategy reduces the number of main memory visits and improves system efficiency, but increases the difficulty of maintaining Cache consistency. The wri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0831
CPCG06F12/0835
Inventor 顾晓峰李青青虞致国魏敬和
Owner JIANGNAN UNIV
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