System and method for realizing chip testing

Abstract

The invention relates to a system for realizing a chip testing, comprising: a simulation IP module used for carrying out a simulation IP test; the digital module that is connected with the analog IP module and is used for testing internal communication signals; the input / output unit library that is connected with the array module and is used for packaging connecting wires; and the test module thatis connected with the analog IP module, the digital module and the input / output unit library and is used for testing the chip. The invention also relates to a method for realizing the chip testing. The system and the method for realizing the chip testing are adopted; under the condition that the number of pins used by the chip is minimum, the problem of errors of DFT related tools is solved, various tests of the chip are realized, test pins do not need to be added, so that the area of the chip is reduced as much as possible, the cost is controlled, the test becomes more flexible, the whole chip can be controlled through input of individual pins, requirements on a test board card of a test machine are correspondingly reduced, the interface is simple, and the cost is reduced.

Description

technical field [0001] The present invention relates to the field of chips, in particular to the field of chip testing, in particular to a system and method for realizing chip testing. Background technique [0002] In the test design of the chip, when there are enough pins, one pin is usually used as the test enable, and several pins are selected as the test mode selection. According to different test modes, the required excitation is input through the pins, and the output Observe and compare. [0003] When doing DFT, you only need to run the script to define the corresponding test pins, confirm the status, and the IO library read in is a pure digital standard IO library with a clear structure definition, and the tool can insert the scan chain by itself and check the scan chain , coverage statistics, etc. [0004] The test enable exists independently, the test mode pins are sufficient, and the pure digital standard IO library is used. The testability design of this type of...

AI Technical Summary

Problems solved by technology

[0004]The test enable exists independently, the test mode pins are sufficient, and the pure digital standard IO library is used. The testability design of this type of circuit should be based on sufficient pins. The IO port is relatively simple, so its applicability is not high, and the disadvantages brought about are too many pins, too large area, and high cost. efficiency

Images