Analog-to-digital converter and three-level switching method applied to SAR ADC

Abstract

The invention discloses an analog-to-digital converter and a three-level switching method applied to an SAR ADC. The method belongs to the technical field of capacitive DACs of SAR ADCs, the whole process is divided into a sampling stage and a conversion stage, and the sampling stage is connected to top polar plates of an upper capacitor array and a lower capacitor array through sampling switchesaccording to input signals VIP and VIN; in the conversion stage, the comparator performs MSB bit-to-LSB bit comparison on the voltages of the top polar plates of the upper and lower capacitor arrays to obtain corresponding digital codes, and controls the connection relationship of the capacitor bottom polar plates in the upper and lower capacitor arrays according to the digital codes; and obtaining an N-bit digital output code through N times of comparison. Different from most published three-level switching methods, a new third reference level Vaq is adopted, and the value of the new third reference level Vaq is equal to one fourth of the reference voltage Vref. Compared with a traditional switching algorithm, the method has the advantages that 99.61% of power consumption of the capacitorsplit type DAC can be reduced, 87.5% of capacitor area is saved, and good compromise between energy efficiency and area saving is achieved.

Description

technical field [0001] The invention belongs to the technical field of capacitive DAC of SAR ADC, and in particular relates to an analog-to-digital converter and a three-level switching method applied to SAR ADC. Background technique [0002] Because most of the circuits of SAR ADC are composed of digital circuits, and there is no operational amplifier, the energy efficiency is very high, and it is compatible with advanced technology. SAR ADCs with medium precision (8-12 bits) and medium sampling rate (<1MHz) are widely used in biomedical electronics, wearable devices, implantable devices, portable devices, and wireless sensor network nodes. The power consumption of SAR ADC mainly comes from capacitor DAC, comparator and digital control logic, and at low speed, the switching power consumed by capacitor DAC occupies a large proportion of the overall power consumption. [0003] In the existing research, a variety of switching algorithms are proposed to reduce the switching...

AI Technical Summary

Problems solved by technology

Among them, the three-level switching algorithm is generally 0.5V due to the introduction of the third reference level ref , the switching algorithm is more flexible, and the switching power consumption of DAC is often low, but the reduction effect of its capacitor area is not ideal[1][2]

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