A Circuit for Accurately Correcting the Duty Cycle of Clock Signal
A technology of clock signal and duty cycle, which is applied in the direction of transforming continuous pulse chains into pulse chain devices with required modes, and can solve problems such as limited, large chip area, and high current
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[0059] see Figure 9 , which is Embodiment 1 of the clock signal duty ratio correction circuit provided in this application. The clock signal duty ratio correction circuit 100 includes an inverter chain 110 , a delay unit 120 , a phase detection unit 130 and a low-pass filter 140 . The input signal CLKIN is input to the input end of the inverter chain 110, and the duty ratio of the input signal CLKIN is adjusted by changing the gate bias voltage of the first CMOS inverter in the inverter chain 110, and the inverter chain 110 outputs the output signal CLKOUT after the duty ratio correction to the outside. The output signal CLKOUT passes through the delay unit 120 to obtain a delayed signal, and the output terminal of the delay unit 120 is called a node VC. The output signal CLKOUT and the delay signal are used as the input of the phase detection unit 130. The phase detection unit 130 outputs an indication signal representing whether the duty ratio of the output signal CLKOUT ...
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