Method for quickly verifying correct connection of FPGA interconnection lines

Abstract

The invention relates to a method for quickly verifying correct connection of FPGA (Field Programmable Gate Array) interconnection lines, which is used for verifying correct connection of the interconnection lines by adopting topological structure comparison on the basis of a form verification thought. Specifically, from two aspects, firstly, in the initial stage of FPGA design, a perfect interconnection line specification is formulated, an interconnection resource generation tool is customized according to the specification, and an interconnection resource file is generated; and 2, in the chip design process, a hierarchical design method is adopted to perform rule naming on all INSTANCE, so that each SWB in the FPGA has a unique identifier, and after the circuit design is successful, a netlist analysis tool is developed to analyze and obtain interconnection resources of an actual circuit. And comparing the two interconnection resource files to find problems existing in the design andrealize verification of the connection correctness of the interconnection lines. According to the method provided by the invention, correct verification of FPGA interconnection line connection can bequickly completed, the coverage rate reaches up to 100%, and the design time is greatly shortened.

Description

technical field [0001] The invention belongs to the field of electronic technology. In particular, the invention relates to a fast verification method for programmable logic device (FPGA) interconnection lines. Background technique [0002] At present, with the continuous improvement of the manufacturing process level of integrated circuits, the feature size of devices is continuously reduced, the scale of FPGA is getting larger and larger, and there are more and more integrated modules, which can realize more complex functions. The current mainstream FPGA is based on the SRAM design, downloads the configuration information to the corresponding configuration RAM, and controls the opening and closing of the corresponding switch through the value of the configuration RAM to realize the connection of the corresponding circuit. FPGA is mainly composed of programmable input and output, programmable interconnection and programmable logic, wherein programmable interconnection incl...

AI Technical Summary

Problems solved by technology

Unlike some ASIC chips that can be designed with automatic layout and routing, the interconnection of FPGA needs to be customized. During the design process, it is easy to have interconnection short circuit and open circuit. How to detect such errors is very difficult. Currently, dynamic The simulation method to verify the correctness of the interconnection is not only very slow, but also has low coverage

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