Multi-layer integrated circuit layout polygon alignment and simplification processing method and device

Abstract

The embodiment of the invention discloses a multi-layer integrated circuit layout polygon alignment and simplification processing method and device. The method comprises the following steps of projecting a plurality of polygons of a multilayer integrated circuit layout to a same layer, and forming a Delaunay triangular mesh according to a Delaunay triangulation algorithm; aligning the Delaunay triangular mesh to each edge of each polygon, calculating the intersection points of the edges of each polygon, and adding the intersection points into the polygon vertexes and the Delaunay triangular mesh nodes to form a first triangular mesh; on the basis, forming the inner and outer auxiliary polygons for clamping the polygons inside and outside each polygon, and controlling the distances betweenthe inner and outer auxiliary polygons and the polygons through the distance thresholds; and aligning and simplifying the edges of each layer of polygons falling between the inner and outer auxiliarypolygons. According to the present invention, the fragmentation problem after the multilayer polygons form the parallel flat plate field domain can be reduced, the unnecessary dense grids are reduced,the analysis and solving time and the required memory of the multilayer integrated circuit are shortened, the gaps among the polygons can be reserved, and the integrated circuit layout shape is basically not changed.

Description

technical field [0001] The invention relates to the field of simplified processing of integrated circuit layout polygons, in particular to a multilayer integrated circuit layout polygon alignment and simplified processing method and device. Background technique [0002] The layout of the integrated circuit is the intermediate link between the schematic diagram of the integrated circuit and the realization of the integrated circuit process, and it is an indispensable and important link. [0003] Since the thickness and layer spacing of the multilayer integrated circuit board are much smaller than the size of the board, the three-dimensional electromagnetic wave calculation field of the multilayer integrated circuit board can be simplified into multiple two-dimensional calculation fields, and the two-dimensional calculation field is the upper and lower The parallel plate field of layer coupling is also the propagation area of ​​electromagnetic waves. The parallel plate field ...

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Problems solved by technology

[0004] However, the inventor found in the process of implementing the present invention that the alignment and simplification of multiple polygons in the layout of multi-layer integrated circuits in the prior art only simplifies single-layer polygons, and unprocessed multi-layer polygons form a parallel flat field field Afterwards, the problem of fragmentation appeared, resulting in dense grids near the fragments when the grids of these fields were subdivided, which increased the solution time and memory of the multilayer integrated circuit analysis to the extent that the final calculation could not be completed, and due to The gap between adjacent polygons is small, reaching the nanometer level. When the existing technology only simplifies a single polygon, it does not consider the overlapping of polygons on both sides of the gap, which may cause a small change in the shape of the polygon during the simplification process. Make adjacent polygons overlap each other, resulting in short circuits between the lines of the integrated circuit layout, with undesirable consequences

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