Vertical structure chip preparation method

Abstract

The invention provides a vertical structure chip preparation method. The method comprises the steps of: S1, sequentially growing a GaN structure comprising an N-type GaN layer, a quantum well layer and a P-type GaN layer on a growth substrate; S2, etching the periphery of the GaN structure until a PN junction is exposed; S3, covering the surfaces of the GaN structure and the PN junction with a passivation film layer; S4, evaporating a bonding metal layer at the surface of the passivation film layer, and exposing the GaN structure through bonding of the bonding metal layer and a supporting substrate; and S5, removing the edge of the GaN structure, manufacturing a groove for cutting, and performing cutting along the groove to obtain a single LED chip. After the edge of the N surface is removed, the PN junction is still covered by the passivation film layer and the bonding metal and is buried in the inner side of the chip, so that the electric leakage influence caused by positive collapseof blade cutting, the electric leakage influence caused by laser cutting energy conduction and the electric leakage risk caused by the use of a finished product in severe environments such as a hightemperature, a high humidity and the like are greatly reduced, and the reliability of the chip and the finished product is improved.

Description

technical field [0001] The invention relates to the technical field of LEDs, in particular to a method for preparing a vertical structure chip. Background technique [0002] In the process of vertical structure chip preparation, the N-side GaN surface after bonding is generally passivated, using SiO 2 or SiN x The insulating film covers the edge of the chip and the PN junction on the GaN side, and the PN junction can be seen from the chip trench. [0003] Such as figure 1 As shown, the GaN structure (including the P-type GaN layer 3 and the 4-N-type GaN layer 4 ) is bonded to the surface of the support substrate 1 through the bonding metal layer 2 , and the passivation film layer 5 covers the GaN structure and the surface of the trench. However, since the PN junction 8 is exposed on the side of the GaN and the surface is only passivated by a layer of SiO2 or SiNx, it is relatively weak, and the passivation layer or GaN is used in the blade cutting or laser scribing (corre...

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the above shortcomings, the present invention provides a method for preparing a vertical structure chip, which effectively solves the problem that the existing vertical structure chip is easily affected by the external environment and causes leakage

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