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Arithmetic lazy flags representation for emulation

A notation and arithmetic technique, applied in software simulation/interpretation/simulation, computing, instrumentation, etc., to solve problems such as reducing the expected performance, delay, and wasting clock cycles of simulation applications

Pending Publication Date: 2019-10-11
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these traditional emulator techniques waste clock cycles by simulating arithmetic flags even when these arithmetic flags are not required for proper execution of the guest application
Since arithmetic sign emulation often occurs while the application is running, traditional emulation techniques can cause unnecessary delays and degrade the expected performance of emulated applications

Method used

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  • Arithmetic lazy flags representation for emulation
  • Arithmetic lazy flags representation for emulation
  • Arithmetic lazy flags representation for emulation

Examples

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Embodiment Construction

[0011] Aspects of arithmetic lazy flag representations for emulation are described for emulating arithmetic instructions designed to be executed by one processor system architecture to be executed by a different processing system architecture such that an application or operating system Can be run by a processor system even if the application or operating system is not designed to be run by the processor system. As used herein, the processor system performing the emulation is referred to as the "host processor system". Instructions received and emulated by the host processor system are called "guest instructions," which are designed to run on a different architecture of the guest processor system than that of the host processor system.

[0012] In an implementation, guest instructions require the use of information stored in certain memory locations of the processor system. For example, when an arithmetic operation of an application is performed by a computing device running ...

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PUM

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Abstract

In aspects of arithmetic lazy flags representation for emulation, a host processor system receives application instructions that are designed for execution by a guest processor system that is different than a processor architecture of the host processor system. A host emulator receives an application instruction that includes an arithmetic operation, determines a result value of the arithmetic operation that is performed on integer values, and determines a first state variable and a second state variable. The host emulator also determines whether a subsequent application instruction will needa derivation of a subset of arithmetic flags based in part on a third state variable. The host emulator can then determine that the subsequent application instruction does not need the derivation of the subset of arithmetic flags, and perform the subsequent application instruction without a determination of the third state variable, thereby reducing processor clock cycles to emulate the application instructions.

Description

Background technique [0001] Computing devices rely on processors to run applications and perform other tasks. Application developers typically design their applications to run on a specific type of processor architecture. Because different computing devices often implement different processor architectures, problems arise when applications designed for one processor architecture are run by computing devices implementing another processor architecture. For example, a host computing device implementing an x86-based processor architecture would experience Encounter problems. These problems arise because the arithmetic flags in one processor architecture generally do not map directly to the arithmetic flags of a different processor architecture. [0002] As a traditional solution, the host computing device uses an emulator, which translates the instructions of the guest application into x86-based instructions that can be run by the host processor architecture. However, emulato...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/455G06F9/30
CPCG06F9/30094G06F9/4552G06F9/30174G06F9/3001G06F9/30043G06F9/30101
Inventor D·J·米霍克卡
Owner MICROSOFT TECH LICENSING LLC
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