Two-phase dynamic synchronous clock generating circuit applied to charge pump system

Abstract

The invention relates to a two-phase dynamic synchronous clock generating circuit applied to a charge pump system. The two-phase dynamic synchronous clock generating circuit comprises a first path ofring oscillator and a second path of ring oscillator. By adoption of the two-phase dynamic synchronous clock generating circuit applied to the charge pump system, when the output clock signals sufferfrom asynchronous phase change, a dynamic synchronization effect is achieved through mutual promotion and acceleration via the two paths of synergistic ring oscillators, so that the circuit can be applied to occasions with relatively high requirements on frequency and phase synchronization, and has a higher application value.

Description

technical field [0001] The invention relates to the technical field of digital chips, in particular to the technical field of clock synchronization, in particular to a two-phase dynamic synchronous clock generation circuit applied to a charge pump system. Background technique [0002] In the digital chip system, the clock signal occupies a very important position. Such as digital-to-analog converter ADC, data interface circuit, charge pump circuit, etc., all need an accurate clock signal. The clock signal is generally generated by an external clock source or crystal oscillator, but when the external clock source cannot provide the required frequency and phase, it is necessary to design a clock generation circuit inside the chip to generate the clock signal. In a standard CMOS process, a ring oscillator is usually used to generate the oscillation frequency. [0003] see figure 1 As shown, it is a schematic diagram of the circuit structure of a ring oscillator in the prior ...

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Problems solved by technology

[0004] see figure 2 As shown, it is a schematic diagram of the circuit structure of a two-phase dynamic synchronous clock generating circuit in the prior art. In this two-phase dynamic synchronous clock generating circuit, an RS flip-flop is added to convert one clock into two inverted clocks, but The two-phase clock generated by this method, due to the delay of the gate-level circuit, will make the phase synchronization effect not good, especially when the frequency is fast and the synchronization requirements are high, it is not applicable

[0005] if used figure 1 and figure 2 The method to generate a two-phase clock, due to the high frequency of the oscillator, a small gate delay may cause a large phase shift between the two clock signals

The charge pump has high requirements for the synchronization of the two-phase non-overlapping clocks. It is necessary to turn on the capacitor on one side and turn off the capacitor on the other side in time. Otherwise, there will be a current leakage problem and the high voltage required by the circuit cannot be output.

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