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A system and a method for quickly building an FPGA digital simulation model

A digital simulation and simulation model technology, applied in the field of FPGA software verification, can solve the problem of high cost of verification and testing labor and time, and achieve the effect of ensuring reusability, enhancing collaboration, and having good application prospects.

Active Publication Date: 2019-05-10
THE GENERAL DESIGNING INST OF HUBEI SPACE TECH ACAD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] At present, there is no efficient and fast method to build FPGA simulation models, which makes FPGA project verification and testing manpower and time costs high, so it is urgent to design a method to quickly build FPGA software digital simulation models

Method used

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  • A system and a method for quickly building an FPGA digital simulation model

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Embodiment Construction

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0033] see figure 1 As shown, the embodiment of the present invention provides a kind of method that quickly builds FPGA digital simulation model, comprises the following steps:

[0034] S1, read the RTL code of the DUT, extract the name of the DUT, the name of the DUT port, bit width, and transmission direction;

[0035] S2, generating a top-level code file of the simulation model according to the acquired information;

[0036] S3, in the top-level code file of the simulation model, instantiate the module under test, the excitation generator module, and the verification result detection module, and realize the connection between the port of the module under test and the port of the excitation generator module and the result detector module; The detector module is used to generate excitation signals, and the verification result dete...

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Abstract

The invention discloses a system and method for quickly building an FPGA digital simulation model, and relates to the technical field of FPGA software verification. The method comprises the followingsteps: reading an RTL code of a tested piece, and extracting the name of the tested piece, the name, the bit width and the transmission direction of a port of the tested piece; generating a top-layercode file of the simulation model according to the acquired information; and in the top-layer code file of the simulation model, the tested piece module, the excitation generator module and the verification result detector are instantiated, the tested piece port is connected with the ports of the excitation generator module and the result detector module, and then a script file operated by the framework is created. According to the scheme, the establishment of the FPGA digital simulation model can be automatically realized, and the problem that the establishment of the existing FPGA software digital simulation model needs to be completed manually is relieved. And the generated simulation model follows a fixed mode, so that verification personnel are helped to quickly build the numerical simulation model, the consistency of codes among the projects is also helped, and the reusability of the codes is ensured.

Description

technical field [0001] The invention relates to the technical field of FPGA software verification, in particular to a system and method for rapidly building an FPGA digital simulation model. Background technique [0002] FPGA digital simulation is divided into pre-simulation and post-simulation. The main purpose is to confirm whether the functions of the design specification are fully realized and whether all functions are correct. There are two goals to be determined in this link: 1. Functional effectiveness: In a complex design, the functions are usually more complicated, whether the code functions written fully meet the requirements of the design specifications. This requires verification engineers to adequately prove the design during the verification process. 2. Functional completeness: whether all functions have been verified. When the functions are complex, it is very important whether all functions are verified. [0003] The digital simulation model runs on the di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
Inventor 石颢陈军花
Owner THE GENERAL DESIGNING INST OF HUBEI SPACE TECH ACAD
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