A design method of a cracker-proof chip and a cracker-proof chip

Abstract

The invention provides a design method of anti-cracking chip, At that time of chip design, A plurality of different layout data are designed according to the same circuit structure, and a plurality ofdifferent layout data are respectively made into corresponding mask templates, and these different types of mask templates are placed in the same exposure window for photolithography, so that the produced die will have different physical structures, but the circuit structure is the same. When encapsulated, encapsulate it into a package that looks the same. When multiple chips are used for layer-by-layer anatomical photography, the probability of obtaining each layer image of the same layout data is very low, and then the circuit structure diagram extracted from these images is different fromthe circuit structure diagram of the original design, so the anti-cracking ability of the chip is improved.

Description

technical field [0001] The invention belongs to the field of chip security design, and in particular relates to a design method of an anti-cracking chip and an anti-cracking chip. Background technique [0002] In the field of chip security design, an important protection goal is to prevent cracking, that is, to prevent crackers from obtaining the chip circuit structure, and obtaining the chip circuit structure requires reverse engineering of the chip. Reverse engineering includes package dissection and die analysis of the chip. Package dissection is very simple, while die analysis is more complicated, including multiple links. The first link is to obtain the layered photos of the die, and the subsequent link is to extract the circuit according to the photos. And analysis, so the key point of reverse engineering is to get the layered photos of the die. In order to obtain the lower layer photo except the top layer, it is necessary to grind or etch the die to remove the upper ...

AI Technical Summary

Problems solved by technology

[0004] The existing chip security design methods are all realized by increasing the degree of confidentiality, such as encrypting the communication process, or adding a maze covering layer on the die, etc., and have not designed security for the characteristics of reverse engineering.

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