A manufacture process of SONOS device
A manufacturing process and device technology, which is applied in the field of SONOS device manufacturing process, can solve the problems that the selection tube and the storage tube do not share the source and drain regions and are susceptible to interference, so as to realize self-aligned etching, reduce the area, and reduce the selection tube effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0024] Described self-aligned SONOS device manufacture process method is in the following embodiment, implementation process is as follows:
[0025] Step 1, see Figure 4 A first oxide layer 17 is formed on the upper end of the P-type substrate 1, and the oxide layer 17 is used to finally form the gate oxide layer 8 of the transistor in the logic region and the gate oxide layer 2 of the selection transistor. A first polysilicon layer 18 and a first silicon nitride layer 22 are sequentially deposited on the first oxide layer 17, and the first polysilicon layer 18 is used to form the select transistor polysilicon gate 5 and the logic region transistor polysilicon Grid 23. The first silicon nitride layer 22 is used as a reserved layer of the CMP (chemical mechanical polishing) stop layer, and its deposited thickness is
[0026] Step 2, see Figure 5 , the photolithography is opened, the first silicon nitride layer 22 is etched, and the first polysilicon layer 18 is implanted...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com