Two-level pipeline architecture based on RISC-V instruction set

Abstract

The invention discloses a two-level pipeline architecture based on an RISC-V instruction set, including a fetch instruction unit, an execution unit, a data read-write unit, a long pipeline data procesunit, an extended Acceleration Interface Coprocessor, Write-back integer general-purpose registers and bus interface units, wherein the instruction fetching unit fetches the instruction and sends theinstruction to the execution unit through the IR register, the PC value of the instruction is sent to the execution unit through the PC register, the execution unit decodes and dispatches the instruction according to the received instruction and the instruction PC value, the execution unit reads and writes back the integer general register through the decoded operand register index, the executionunit dispatches instructions to each transport module for operation, the execution unit writes back the result of the instruction operation to the write-back integer general register, the bus interface unit is used for auxiliary instruction transmission, and the two-stage pipeline architecture is adopted in the processor core, so as to reduce the cost of the processor core architecture and improve the performance of the processor.

Description

technical field [0001] The invention relates to a low-power processor core architecture, in particular to a two-stage pipeline architecture based on a RISC-V instruction set. Background technique [0002] In the traditional classification of computer architecture, processor applications are divided into three fields, namely: server field, PC field and embedded field. At present, in the field of servers and PCs, the x86 architecture is a well-deserved giant, and no instruction set architecture can shake its monopoly position. In recent years, with the further development of various new technologies, the embedded field itself has been developed into several different subfields. First of all, with the development of smartphones (Mobile Smart Phone) and handheld devices (Mobile Device), the mobile field has gradually developed into an independent field that can match or even surpass the PC field. It is mainly composed of ARM's Cotex-A series processor architecture. monopolized...

AI Technical Summary

Problems solved by technology

[0013] 1. The licensing cost of the ARM commercial architecture core is too high

[0014] 2. Low processor performance

[0015] 3. Since there is no cache but only ITCM, if enough instruction codes are stored, the cost of the chip will increase if the SRAM of ITCM is too large; conversely, if the SRAM of ITCM is small, it cannot carry enough instruction codes

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