Two-dimensional semiconductor material negative capacitance field effect transistor and preparation method thereof

Abstract

The invention discloses a two-dimensional semiconductor material negative capacitance field effect transistor and a preparation method thereof; a two-dimensional alloy semiconductor material HfZrSe2 is adopted as a channel material, and the surface of the channel material is oxidized in air to generate HfZrO2, and then annealing is carried out to obtain an HfZrO2 dielectric layer with a ferroelectric property; a high-k gate dielectric layer is deposited on the dielectric layer, and a gate dielectric with a mixed structure is formed. By means of the device structure, high gate dielectric and channel two-dimensional semiconductor material interfaces can be obtained, the deterioration of the interface state on the sub-threshold characteristic is reduced, and the super-steep sub-threshold slope is easily obtained; meanwhile, the high-k gate dielectric on the upper layer can protect the HfZrO2 dielectric of the ferroelectric characteristics below, so that the dielectric is isolated from theair, and the stability of the device is greatly improved. The device is simple in preparation process and large-scale production can be realized.

Description

technical field [0001] The invention belongs to the technical field of nanoelectronics, and in particular relates to a two-dimensional semiconductor material negative capacitance field effect transistor and a preparation method thereof. Background technique [0002] With the reduction of traditional MOSFET feature size and the improvement of integration, the operating voltage and threshold voltage of the device are gradually reduced. The ensuing short-channel effect is more obvious, and the drain-induced barrier reduction and source-drain band-band tunneling will increase the leakage current and power consumption of the device. In addition, due to the current mechanism of MOSFET thermal emission, its subthreshold slope is limited by the thermal potential, and there is a theoretical limit of 60mV / dec, which cannot be reduced with the reduction of device size, which leads to a further increase in the leakage current of the device and power consumption. The problem intensifies...

AI Technical Summary

Problems solved by technology

However, most of the gate dielectric materials of field effect transistors based on two-dimensional materials are still realized by atomic layer deposition. The interface state between the obtained gate dielectric and the two-dimensional semiconductor material is relatively serious, which will deteriorate the subthreshold slope of the device.

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