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Method of manufacturing semiconductor element

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of manufacturing process technology bottleneck and high cost, and achieve the advantages of increasing mobility, reducing parasitic capacitance, and improving driving current. Effect

Active Publication Date: 2018-08-28
POWERCHIP SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the current technology for reducing the size of components is limited by factors such as manufacturing process technology bottlenecks and high costs, it is necessary to develop other technologies that are different from reducing components to improve the drive current of the components.

Method used

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  • Method of manufacturing semiconductor element
  • Method of manufacturing semiconductor element
  • Method of manufacturing semiconductor element

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Embodiment Construction

[0056] In the following embodiments, when the first stress layer is a tensile stress layer, the second stress layer is a compressive stress layer; when the first stress layer is a compressive stress layer, the second stress layer is a tensile stress layer. In this embodiment, the first stress layer is a tensile stress layer and the second stress layer is a compressive stress layer as an example for illustration, but the present invention is not limited thereto.

[0057] In addition, the thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

[0058] In addition, in order to easily describe the relationship between one component or feature and another component or feature depicted in the drawings, for example, "under", "under", "lower part", "under", etc. may be used herein. Spatially relative terms for "on," "abo...

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Abstract

The invention discloses a method of manufacturing a semiconductor element. The method comprises the following steps: respectively forming a first stress layer and a second stress layer on a substrate;forming a buffer layer on the first stress layer and the second stress layer; performing an injection manufacturing process on the substrate, to form a precut surface in the substrate on the lower part of the first stress layer and the second stress layer; performing joining treatment, to join a carrier plate on the buffer layer; performing heat treatment, to separate a part of the substrate fromthe precut surface; performing the previous manufacturing process on a precut surface on another part of the substrate.

Description

technical field [0001] The present invention relates to a manufacturing method of an integrated circuit, and in particular to a manufacturing method of a semiconductor element. Background technique [0002] During the development of semiconductor devices, the size of the device (ie, gate width and channel length) is often reduced to achieve high-speed operation and low power consumption. However, since the current technology for reducing device size is limited by factors such as manufacturing process technology bottlenecks and high costs, it is necessary to develop other technologies different from device reduction to improve the driving current of the device. [0003] Therefore, the industry currently proposes a method of controlling strain to increase device performance, so as to overcome the limit of device miniaturization. The method of controlling the strain refers to forming a stress layer in the semiconductor element, so that the channel region of the element is stra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L29/78
CPCH01L21/8238H01L29/7842
Inventor 李世平陈昱安黄绣雯张娟华
Owner POWERCHIP SEMICON MFG CORP
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