High electrical performance chip packaging structure and manufacturing method

Abstract

The invention discloses a chip packaging structure with high electrical performance and a manufacturing method that can withstand the test of harsh environments. The packaging structure retains a part of the dielectric layer or adds an inorganic oxide layer on the front pad of the chip. Due to the dielectric layer or The dielectric constant of the inorganic oxide layer is low, and the experimental results show that the stress at the opening is significantly reduced, thereby reducing the delamination phenomenon between the metal wiring layer and the chip pad, and improving the packaging yield; at the same time, the inorganic oxide layer and the outer insulating layer are parallel , at the corners on the pads and at the corners of the front of the wafer and the first opening, the thickness is uniform, the dielectric constant is low, and the insulation of the product is improved, thereby preventing the occurrence of leakage failure, and the single-layer insulation layer is set in the prior art Compared with the present invention, the two insulation layers whose inner layers are inorganic oxide layers are not easily affected by moisture absorption, and have stronger moisture resistance.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip packaging, in particular to a chip packaging structure with high electrical performance and a manufacturing method. Background technique [0002] figure 1 A known packaging structure of a chip is shown. The chip takes an image sensor as an example and includes an image sensor chip 100. The functional surface of the image sensor chip includes an image sensing area 101 and several pads around the image sensing area. 102; the opening, the opening extends from the back to the functional surface, and the bottom of the opening exposes the side of the pad; the metal wiring layer 130, the metal wiring layer is located on the inner wall and back of the opening, electrically connected to the pad; the insulating layer 120, The insulating layer is located between the metal wiring layer and the image sensor chip, and exposes the welding pad; a number of solder bumps 140, the solder bumps are locate...

AI Technical Summary

Problems solved by technology

In other structures, there are also technical solutions in which the bottom of the opening exposes the back of the pad. Since the metal wiring layer is electrically connected to the back of the pad, its electrical performance is better, and the manufacturing process is simple. It only needs to remove the insulating layer on the back of the pad. There is no need to penetrate the welding pad; however, with this structure, experiments have proved that the stress at the corner where the metal wiring layer contacts the welding pad is relatively large. The variable is very large. Due to the pulling of the solder mask layer, the solder pad and the metal wiring layer are prone to delamination, which makes it unable to meet the higher requirements of the application environment.

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