Comparator circuit for high speed pipeline adc

Abstract

The present invention provides a comparator circuit suitable for high-speed pipeline ADC, including a switched capacitor circuit, a pre-amplification circuit and a latch circuit, the pre-amplification circuit includes a pre-amplifier, an adjustable resistance device, a first switch and a second switch, and a lock The storage circuit includes a differential static latch, a first capacitor, a second capacitor and a third switch, the first output end of the switched capacitor circuit is connected to the non-inverting input end of the pre-amplifier, and the second output end is connected to the inverting input end of the pre-amplifier, The inverting output terminal of the pre-amplifier is connected to the positive input terminal of the differential static latch through the first switch; the non-inverting output terminal of the pre-amplifier is connected to the negative input terminal of the differential static latch through the second switch, and the positive output terminal of the differential static latch is The terminal is connected to its positive input terminal through the first capacitor, the negative output terminal is connected to its negative input terminal through the second capacitor, and the third switch is arranged between the positive output terminal and the negative output terminal of the differential static latch. The invention can increase the transmission rate of the sampling phase and the establishment phase.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuits, and in particular relates to a comparator circuit suitable for a high-speed pipeline ADC (Analog-to-Digital Converter, analog-to-digital converter). Background technique [0002] The comparator in the form of switched capacitors is one of the key units in the pipeline analog-to-digital converter. Currently, common comparators include comparators with dual-capacitor architecture and single-capacitor architecture. Among them, the comparator with dual-capacitor architecture is as figure 1 as shown, figure 1 The corresponding switch in the figure 2 Corresponding to the control signal φ1 or φ2 to control its on-off, the control signal φ1 is the sampling phase sequence, and φ2 is the establishment phase sequence. In the sampling phase, when the control signal φ1 is at a high level, each switch controlled by it is turned on, and the input signal V IP and V IN Corresponding to be col...

AI Technical Summary

Problems solved by technology

[0004] Although the transfer rate of the comparator of the single-capacitor architecture is relatively high, which can increase the conversion rate of the pipeline ADC, the comparator of the single-capacitor architecture is in the sampling phase, and the input signal is sent to the input terminal of the latch (V IP with V LN , or V IN with V LP The sampling network between ) has constituted a second-order system. For the pipeline MDAC sampling network that only includes switch resistors and sampling capacitors, it belongs to the first-order system. There is a problem of bandwidth mismatch when the two are used together.

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