A method and system for synchronizing read data based on ddr

Abstract

The invention discloses a DDR-based reading data synchronization method and system. The method uses a frequency divider to input a data strobe signal half-inpu-dqs-n as a DDR interface DQS signal, a sampling clock internal-clk serves as a sampling clock in a DDR controller, a transition clock is set up as a synchronous clock between the DDR interface DQS signal and the sampling clock in the DDR controller, and the synchronous clock achieves the synchronization of the sampling clock in the DDR controller and an input color outside the DDR and achieves asynchronous transmission of DDR interfaceDQS domain data and domain data of the sampling color in the DDR controller. According to the method and the system, the building time and the retention time of a DQS domain and a sampling color domain in the DDR controller can be satisfied to the maximum extent, the synchronization problem of the DDR reading data is solved with a very small delay, and the method and the system no longer rely on the FIFO technology.

Description

technical field [0001] The invention relates to the technical field of DDR memory data reading and writing, in particular to a DDR-based reading data synchronization method and system. In the present invention, DDR refers to DDR3 memory. Background technique [0002] DDR (DDR memory) is the habitual abbreviation of DDR SDRAM. Its full name should be double-rate synchronous dynamic random access memory, among which: DDR is the abbreviation of Double Data Rate, and SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory. The advantages of DDR are large storage capacity, low cost, mature interface, and high access rate can be achieved during parallel burst access. [0003] DDR memory is developed on the basis of SDRAM memory and still uses the SDRAM production system. Therefore, for memory manufacturers, it is only necessary to slightly improve the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce co...

AI Technical Summary

Problems solved by technology

[0010] As a high-speed interface, the frequency of DDR is constantly increasing. When the clock is higher than 800Mhz, the timing problem becomes a very large bottleneck in the design of a DDR controller. In particular, when DDR reads data, the DQS (data selection pulse) returned from DRAM and The synchronization problem of the sampling clock inside the DDR controller restricts the high-speed transmission of DDR

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