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Preparation method and structure of three-dimensional memory

A memory, three-dimensional technology, applied in the direction of electric solid devices, semiconductor devices, electrical components, etc., can solve the problems such as the increase of electrode resistance of the metal gate 17 and the thickness loss of the tungsten metal gate 17, and achieve the effect of increasing the thickness

Inactive Publication Date: 2018-02-16
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Wherein the real effective area of ​​Al2O3 is the position in contact with ONOP, so there are the following two problems in the prior art: as figure 2 A basic unit of the storage particle shown, it is found that when the dummy gate thickness of the storage unit prepared by the ONOP process is constant, the thickness of the tungsten metal grid 17 has a certain loss due to the existence of the aluminum oxide dielectric layer 18, which will Cause the resistance of metal grid 17 electrode to increase; In addition, as Figure 9 As shown, when the contact hole 20 is formed in the step region, the thinning of the tungsten metal gate 17 brings a greater challenge to the etching process of the contact hole 20 in the step region.

Method used

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  • Preparation method and structure of three-dimensional memory

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Embodiment 1

[0040] refer to Figure 10-14 As shown, Embodiment 1 of the present invention proposes a method for preparing a three-dimensional memory, which is characterized in that it includes the following steps:

[0041] Such as Figure 10 As shown, a substrate 20 is provided, and an array storage area 21 and a peripheral circuit area 22 of a three-dimensional memory are formed on the substrate 20;

[0042] The display storage area 21 includes a multi-layer stack structure in which silicon oxide layers 23 and silicon nitride layers 24 are alternately formed on the substrate 20; the number of layers of the stack structure is greater than or equal to 48 layers, preferably 48 layers or 64 layers , 80 floors, 96 floors, 112 floors or 128 floors.

[0043] forming a storage core area 25 and a stepped area 26 with a multi-layer stack structure;

[0044] Such as Figure 10 As shown, a plurality of through holes 27 are formed in the storage core area 25;

[0045] Such as Figure 11 As shown,...

Embodiment 2

[0051] Embodiment 2 of the present invention proposes a method for preparing a three-dimensional memory, which is characterized in that it includes the following steps:

[0052] Such as Figure 10 As shown, a substrate 20 is provided, and an array storage area 21 and a peripheral circuit area 22 of a three-dimensional memory are formed on the substrate 20;

[0053] The display storage area 21 includes a multi-layer stack structure in which silicon oxide layers 23 and silicon nitride layers 24 are alternately formed on the substrate 20;

[0054] A multilayer stack structure is formed into a storage core region 25 and a step region 26; a step region 26 is formed on at least one side of the multilayer stack structure so that a part of the upper surface of each silicon nitride layer 24 is exposed to step area 26;

[0055] Such as Figure 10 As shown, an insulating layer 36 with a flat surface is formed on the substrate 20 to cover the peripheral circuit area 22 and the array st...

Embodiment 3

[0062] Embodiment 3 of the present invention proposes a method for manufacturing a three-dimensional memory. In this embodiment, parts different from the above embodiments will be described, and the same parts will not be repeated.

[0063] The forming of the contact hole 34 electrically connected to the peripheral circuit region 22 includes patterning the insulating layer 36 on the peripheral circuit region 22, etching and metal filling to form a contact hole 34 electrically connected to the peripheral circuit region 22. A plurality of first contact holes 34 .

[0064] The formation of the contact hole 35 electrically connected to the metal gate 33 includes patterning the insulating layer 26 on the array storage area 21, etching and filling with metal to form a contact hole 35 with each metal gate of the array storage area 21. A plurality of second contact holes 35 electrically connected to the gate 33 .

[0065] The metal material used for the metal filling is tungsten.

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Abstract

The invention provides a preparation method and a structure of a three-dimensional memory. An ONOP process is changed into an AONOP process; equivalently, after a conductive channel in an array storage region is etched, aluminum oxide, silicon dioxide, silicon nitride, silicon dioxide and a polysilicon stacked layer are prepared through an atomic layer deposition mode separately; therefore, afterthe pseudo gate is removed by a wet process, atomic layer deposition of aluminum oxide is not needed; and consequently, the tungsten metal gate thickness in the three-dimensional memory is increased,the metal gate resistance is lowered, and the selection ratio difficulty of tungsten contact hole etching in a stage region is lowered.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a preparation method and structure of a three-dimensional memory. Background technique [0002] With the continuous improvement of market demand for memory capacity, the number of memory cells that can be provided per unit area by traditional memory based on planar or two-dimensional structures is approaching the limit, which cannot further meet the market demand for larger capacity memory. Just like several bungalows built on a limited plane, these bungalows are neatly arranged, but as the demand continues to increase, the number of bungalows continues to blow out, but in the end this limited plane can only accommodate a certain number of bungalows. Cannot continue to increase. Planar memory is approaching its practical expansion limit, which brings severe challenges to the semiconductor memory industry. [0003] In order to solve the above difficulti...

Claims

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Application Information

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IPC IPC(8): H01L27/11521H01L27/11551H01L27/11524
CPCH10B41/35H10B41/20H10B41/30
Inventor 宋豪杰徐强李广济邵明夏志良霍宗亮
Owner YANGTZE MEMORY TECH CO LTD
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