Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device sequentially comprises a silicon substrate, one or more NAND strings formed at the upper partof the silicon substrate, one or more peripheral devices formed at the upper parts of the NAND strings, a monocrystal silicon layer formed at the upper parts of the one or more peripheral devices, andone or more first interconnection layers formed between the one or more peripheral devices and between the one or more NAND strings from bottom to top, wherein the peripheral devices are bonded withan array device through a bonding interface. The preparation process that two devices are affected by each other when prepared can be avoided through separating preparation of the array device and theperipheral devices, so that the problem of temperature limitation of preparation of the front layer to preparation of the back layer in the prior art is solved, thereby obtaining good performance ofthe peripheral devices. In addition, the peripheral devices are superposed on the array device, thereby achieving high device density.

Description

technical field [0001] The invention relates to a semiconductor device and a preparation method thereof, in particular to a semiconductor device forming a 3D NAND flash memory and a preparation method thereof. Background technique [0002] With the continued emphasis on highly integrated electronics, there is a continuing need for semiconductor memory devices that operate at higher speeds and lower power and have increased device densities. To this end, devices with smaller dimensions and multilayer devices with transistor cells arranged in horizontal and vertical arrays have been developed. 3D NAND is an emerging type of flash memory developed by the industry. It solves the limitations of 2D or planar NAND flash memory by stacking memory particles together. [0003] The planar structure of NAND flash memory is approaching its actual expansion limit, which brings severe challenges to the semiconductor memory industry. The new 3D NAND technology stacks multiple layers of da...

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Problems solved by technology

[0006] However, the disadvantage of the above-mentioned patented technology is that the above-mentioned vertical channel memory device is fabricated sequentially on only one Si substrate layer, so the temperature of the subsequent layers must be limited during fabrication, otherwise the previously fabricated ones will be destroyed due to the high temperature. Layer produces ion diffusion, which affects product performance

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