A twisted-pair shared central capacitor array and its layout design method

Abstract

The invention relates to a twisted-pair sharing center capacitor array and a layout design method thereof. The capacitor array is a line capacitor array composed of n unit capacitors, and a sharing center of the unit capacitor array is used as the original point, a corresponding channel at the original point is a horizontal channel 0, the unit capacitors are in twisted-pair symmetric arrangement by taking the horizontal channel 0 as a symmetric line, multiple unit capacitors form a significant bit capacitor; the significant bit capacitor comprises an upper pole plate and an lower pole plate; the upper pole plate is connected with a ground wire gauze G, the lower pole plate is connected with a signal end wire gauze S; even bit horizontal channels are in wiring connection with the upper poleplate of the significant bit capacitor, and the odd bit horizontal channels are in wiring connection with the lower pole plate of the significant capacitor. The linear performance of the circuit andthe precision performance of the ADC are improved through the twisted-pair sharing center capacitor array.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a twisted-pair shared central capacitor array and a layout design method thereof. Background technique [0002] In low-power analog-to-digital converters (ADC) and switched capacitor circuits, the accuracy of on-chip unit capacitance is one of the key factors affecting circuit performance. For example, if figure 1 As shown, the capacitor array schematic diagram of the successive comparison (SAR) ADC, the switched capacitor array, as the sub-analog-to-digital converter (sub-DAC) of the successive comparison (SAR) ADC, is an important part that affects the accuracy and speed of the ADC. [0003] Ideally, the value of the unit capacitance in the figure increases strictly according to the multiple ratio. However, in the actual tape-out production, affected by factors such as process gradients and uneven thickness of the oxide layer, there will be a systematic mismatch in the un...

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Problems solved by technology

figure 2 The disadvantage of the layout method shown is that it does not consider the impact of routing after placement

[0006] like image 3 As shown, it is a schematic diagram of the violation of the signal coupling rule by the spiral layout method. The unit capacitance wiring of the S2 path crosses the ground wire, and a parasitic capacitance for signal coupling is formed at the intersection point, thereby affecting the linear performance of the switched capacitor array, and Affecting the accuracy performance parameters of SAR ADC (INL / DNL)

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