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Chip debugging method, device, storage medium and processor

A debugging method and a technology for configuring registers, which are applied in the field of integrated circuits, can solve problems such as low chip efficiency, and achieve the effects of solving low efficiency, alleviating the impact on area, and avoiding operation

Active Publication Date: 2020-03-17
CHIPONE TECH BEIJINGCO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main purpose of the present invention is to provide a chip debugging method, device, storage medium and processor, to at least solve the problem of low efficiency of chip debugging

Method used

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  • Chip debugging method, device, storage medium and processor
  • Chip debugging method, device, storage medium and processor
  • Chip debugging method, device, storage medium and processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] The embodiment of the present invention provides a chip debugging method.

[0029] figure 1 It is a flowchart of a chip debugging method according to an embodiment of the present invention. Such as figure 1 As shown, the method includes the following steps:

[0030] Step S102: Select the first processing module corresponding to the target debugging signal.

[0031] In the technical solution provided in step S102 of the present application, the first processing module corresponding to the target debug signal is selected, wherein the target debug signal is used to debug the target chip.

[0032] This embodiment can be used in the development of integrated circuits, and the debugging method of this embodiment can be used in the early stage of circuit design. In the debug mode (DEBUG), select the first processing module corresponding to the target debug signal. The target debugging signal is a signal required for debugging the target chip, and may be provided by a corresponding f...

Embodiment 2

[0067] The technical solutions of the present invention will be described below in conjunction with preferred embodiments. Specifically, the target bus is an SPI bus for illustration.

[0068] figure 2 It is a schematic diagram of a chip debugging structure according to an embodiment of the present invention. Such as figure 2 As shown, in the normal working state, the external SPI[3:0] bus can read and write (r / w) the internal registers of the chip and send commands cmd through the chip port PAD. Among them, the SPI[3:0] bus Including 0, 1, 2, and 3 four lines. In the debug mode (assuming that the chip structure is composed of two levels), the gate block 1 (mask1) is controlled under the control signal ctrl through the configuration register REG to select the processing module where the required signal is located; through the configuration register REG under the control signal ctrl Gate block 2 (mask2_1) selects the signal in the processing module for output; configures REG t...

Embodiment 3

[0072] The embodiment of the invention also provides a chip debugging device. It should be noted that the chip debugging device of this embodiment can be used to execute the chip debugging method of the embodiment of the present invention.

[0073] Figure 4 It is a schematic diagram of a chip debugging device according to an embodiment of the present invention. Such as Figure 4 As shown, the device includes: a selection unit 10, an output unit 20, a control unit 30, and a debugging unit 40.

[0074] The selection unit 10 is configured to select the first processing module corresponding to the target debug signal, where the target debug signal is used to debug the target chip.

[0075] The output unit 20 is configured to output the target debugging signal through the first processing module.

[0076] The control unit 30 is configured to control the target debugging signal to be output to the target chip when the target debugging signal is allowed to be output to the target chip, w...

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Abstract

The invention discloses a chip debugging method and device, a storage medium and a processor. The method comprises the following steps: selecting a first processing module corresponding to a target debugging signal, wherein the target debugging signal is used for debugging a target chip; outputting the target debugging signal through the first processing module; in a condition that the target debugging signal is allowed to be output to the target chip, controlling the target debugging signal to be output to the target chip, wherein the target chip is connected with a target bus; and debuggingthe target chip through the target bus on the basis of the target debugging signal. The invention has the effect that the chip debugging efficiency is improved.

Description

Technical field [0001] The present invention relates to the field of integrated circuits, and in particular to a method, device, storage medium and processor for debugging a chip. Background technique [0002] At present, in the development process of large-scale integrated circuits, necessary debugging methods need to be added in the early stage of circuit design to test the reliability of the chip and evaluate and analyze circuit problems. The debugging method usually used at present is to increase the number of chip ports (IO), export any chip internal signal to the debug (DEBUG) port through a certain logic design, and observe the port signal to verify the actual test Analysis and evaluation of problems that arise. [0003] For the above methods, increasing the number of ports on the chip will have a certain negative effect on the chip area, and complicate the back-end process in the integrated circuit development process, resulting in low chip debugging efficiency; while in o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
Inventor 张路高晨明
Owner CHIPONE TECH BEIJINGCO LTD
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