Circuit structure and method for expanding number of operation times of memory

Abstract

The invention provides a circuit structure and method for expanding the number of operation times of a memory. The circuit structure comprises an N-bit cycle counter circuit, N address generation circuits and a memory array; the N address generation circuits are connected with the N-bit cycle counter circuit; the memory array is connected with the N address generation circuits; N times of operations on a memory word are dispersed into N different memory words; therefore, excessive operation on a memory word is avoided; when the power is off every time, the state of a trigger circuit is storedin a non-volatile phase change memory; when the power is on every time, the data in the non-volatile phase change memory is read out; therefore, the trigger circuit and the N-bit cycle counter circuitrecover to the state before the power is off; and thus, balanced operation of the memory words in any condition can be realized. By means of the circuit structure and method for expanding the numberof operation times of the memory provided by the invention, the problem that a phase change memory cannot realize the reading, writing and erasing balance of each memory unit in the prior art can be solved.

Description

technical field [0001] The invention belongs to the application field of integrated circuit memory, and in particular relates to a circuit structure and method for extending memory operation times. Background technique [0002] With the rapid development of informatization, networking and intelligence, the embedded storage system has become an important node of data processing. The number of times of writing and erasing is limited. When the number of times of reading, writing and erasing reaches a certain limit, the data stored in the memory will become unreliable. Moreover, with the improvement of integrated circuit technology, charge-type memories such as DRAM and Flash Memory generally have defects such as low write durability and low performance of memory cells, which have encountered development bottlenecks and limited their wide application. [0003] In order to increase the lifespan of the memory and make each bit of the memory cell obtain read-write and erase-balanc...

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a circuit structure and method for extending the number of operations of the memory, which is used to solve the problem that the phase change memory in the prior art cannot achieve read-write-erasing balance of each storage unit. question

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